高性能元件和超低功耗系統對於人工智能(AI)和物聯網(IoT)應用等新興需求非常重要，而降低電源電壓(Supply voltage)是實現較低靜態和動態功耗的有效方法之一。然而，降低電源電壓會降低半導體元件的導通電流(Ion)，因此陡坡元件(Steep slope device)對於超低功率系統應用是必需的，具有更好的Ion/Ioff比率的負電容場效電晶體(Negative Capacitance Field Effect Transistor, NCFET)，為有機會實現高效率開關和超低功率系統的前瞻元件之一。

本文利用TCAD 軟體的Poisson-Schrodinger solver，並且結合穩態的Landau-Khalatnikov方程式，建立了負電容場效電晶體的數值模擬流程架構，並且分析了負電容場效電晶體的微縮性(Scalability)、對元件尺寸變化的靈敏度(Sensitivity)和變異度(Variability)。在微縮性的研究中，我們研究了負電容鰭狀場效電晶體(NC-FinFET)和負電容完全空乏型場效電晶體(NC-FDSOI)微縮至2奈米技術節點。我們提出TCAD元件模擬驗證，對於負電容鰭狀場效電晶體使用固定鰭狀厚度(Wfin)，及負電容完全空乏型場效電晶體使用固定通道厚度(Tch)，負電容效應可以使兩種傳統的場效電晶體的閘極通道長度微縮至兩奈米技術節點。而負電容鰭狀場效電晶體和負電容完全空乏型場效電晶體在兩奈米技術節點下，表現出關閉電流(Ioff)小於100 nA/µm，而且對比相同節點下的鰭狀場效電晶體和完全空乏型場效電晶體，負電容效應提升其導通電流約10%~29%。

其次，我們分析了元件結構參數和鐵電參數，包括殘餘極化(remnant polarization, P0)、矯頑場(coercive field, EC)和鐵電層厚度(ferroelectric layer thickness, TFE)等參數，對次臨界擺幅(subthreshold swing, SS)和電壓增益(Voltage gain, Av)的影響。

最後，針對變異度的研究，我們分析了考慮線邊緣粗糙度(line edge rouoghness, LER)和功函數變異度(Work function variation, WFV)，對負電容完全空乏型場效電晶體(NC-FDSOI)和完全空乏型場效電晶體(FDSOI)的臨界電壓(Vt)和切換時間(Switching time, ST)變異度之影響。在考慮線邊粗糙度的影響下，相較於一般完全空乏型場效電晶體(σVt = 16.2 mV)，負電容完全空乏型場效電晶體具有有較小的臨界電壓之變異度(σVt = 3.8 mV)；而考慮金屬功函數變異度的影響下，負電容完全空乏型場效電晶體有和一般完全空乏型場效電晶體差不多的臨界電壓變異度。換句話說，負電容效應可以抑制線邊粗糙度導致的臨界電壓變異度，但是無法抑制金屬功函數變異所導致的臨界電壓變異度。然而，一般完全空乏型場效電晶體，其線邊粗糙度和金屬功函數變異度所導致的臨界電壓變異度是差不多的，但無論是完全空乏型場效電晶體或是負電容完全空乏型場效電晶體，考慮線邊粗糙度下的切換時間變異度，都會大於金屬功函數變異度所導致的切換時間變異度。這是因為考慮金屬功函數變異度下，過度電荷(Transition charge, ∆Q)和等效驅動電流(Effective drive current, Ieff)是呈現正相關性；而考慮線邊粗糙度下，過度電荷和等效驅動電流是呈現負相關性。

High-performance devices and ultra-low power systems are important for emerging demands of artificial intelligence (AI) and Internet-of-Thing (IoT) applications. Reducing supply voltage is an efficient method to achieve lower static and dynamic power. However, reducing supply voltage degrades the on-state current for the semiconductor devices. Therefore, the steep slope device is necessary for the low power system application. Negative capacitance FET (NCFET) with better Ion/Ioff ratio is a promising candidate to achieve energy-efficient switching and ultra-low power system.

In this dissertation, we establish the numerical simulation framework for NCFET by using TCAD coupled with 1D steady state Landau-Khalatnikov equation and then analyze the scalability, sensitivity, and variability of negative capacitance FETs. First, for the scalability study, we analyze the negative capacitance FinFET and FDSOI (NC-FinFET and NC-FDSOI) for technology nodes down to 2nm. We present TCAD simulation evaluation, with fixed Wfin for FinFET and Tch for FDSOI, negative capacitance concept enables FinFET and FDSOI scaling to 2 nm node. NC-FinFET and NC-FDSOI at 2 nm node show Ioff < 100 nA/μm and 10% ~ 29% higher Ion compared with 2nm FinFET (97 μA/μm Ioff) and FDSOI (46 μA/μm Ioff). NC-FDSOI exhibits similarly strong back-gate bias effects on Ioff and Ion compared with FDSOI.

Second, we analyze the sensitivity and the impact of the device structures, device parameters, and ferroelectric parameters including remnant polarization (P0), coercive field (EC) and thickness of the ferroelectric layer (TFE) on the subthreshold swing (SS), voltage gain (AV). Finally, for the variability study, we analyze the threshold voltage (Vt) and switching time (ST) variations of NC-FDSOI and FDSOI considering line-edge roughness (LER) and work function variation (WFV). Compared to FDSOI, NC-FDSOI exhibits smaller LER induced Vt variations (σVt = 3.8 mV) and comparable WFV induced Vt variations (σVt = 16.2 mV). LER induced σVt can be suppressed by negative capacitance, while WFV induced σVt cannot be suppressed by negative capacitance. However, for both NC-FDSOI and FDSOI, LER induced ST variations are larger than the WFV induced ST variations. This is because transition charge (∆Q) and effective drive current (Ieff) are positively correlated for considering WFV and negatively correlated for considering LER.

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