以波動數位濾波器為基礎的類比仿真器之管線化設計及其時間與硬體的最佳化

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研究生：	葉生元 Conan Yeh
論文名稱：	以波動數位濾波器為基礎的類比仿真器之管線化設計及其時間與硬體的最佳化 Timing and Resource Optimization of Pipelined Analog Emulator Based on Wave Digital Filters
指導教授：	劉建男 Chien-Nan Liu
口試委員:
學位類別：	碩士 Master
系所名稱：	資訊電機學院 - 電機工程學系 Department of Electrical Engineering
論文出版年：	2015
畢業學年度：	103
語文別：	中文
論文頁數：	52
中文關鍵詞：	波動數位濾波器、管線化、時間最佳化、硬體最佳化
外文關鍵詞：	Wave Digital Filter, Pipeline, timing optimization, resource optimization
相關次數：	點閱：13 下載：0
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波動數位濾波器(wave digital filter)可用數位電路模擬類比元件的行為，而以此為基礎的類比仿真器(analog emulator)使得類比與數位混合訊號(analog and mixed signal, AMS)電路的模擬及驗證變得可行，此類比仿真器在波動數位濾波器的基礎上，將時間域中的電阻，電容，電壓源等元件轉至波動數位域，並使用串聯及並聯關係(配線器)以樹狀結構表示出整個電路，再以波的形式輸入訊號以模擬電路行為。為了降低此類比仿真器的硬體成本並提升效能，本論文中提出了一個對此樹狀結構管線化的方法，並隨著關鍵路徑長度限制，自動設計出限制下硬體最佳化的管線化設計，且此方法設計出之結構在模擬後結果可以看出，本論文所提出的方法確實可以在路徑時間限制下，設計出管線化電路結構，以符合要求並最佳化硬體數量。

Wave Digital Filter (WDF) can simulate analog element with digital circuit. The analog emulator based on WDF makes the simulation and verification of mixed signal circuit feasible. This emulator transforms resistor, capacitor, inductance and resistive voltage source into wave digital domain and connect them with either serial or parallel adaptor to represent circuit architecture.
In order to reduce this analog emulator’s hardware costs and improve efficiency. This thesis proposes an algorithm to generate pipelined WDF tree-like structure. According to different critical path constrain, the pipelined hardware resource can be optimized by the algorithm. From the simulation results on several cases, the proposed method can generate the required pipelined WDF structure that meets the timing constrains and optimize the hardware resource.

摘要    V
Abstract    VI
目錄    VIII
圖目錄    X
表目錄    XII
第一章 緒論    1
1-1研究動機    1
1-2相關研究    2
1-2-1 場列式可程式邏輯閘陣列(FPGA)    2
1-2-2 場列式可程式類比陣列(FPAA)    3
1-3論文結構    4
第二章　背景知識    5
2-1波動數位濾波器簡介(Wave Digital Filter)    5
2-1-1RLC電路之數位濾波器模型    5
2-1-2波動數位濾波器中的元件模型    6
2-1-3配線器(Adaptor)    9
2-1-4 波動數位樹狀結構(Wave digital tree structure)    11
2-2管線化方法(Pipeline)    14
2-2-1完全管線化(Fully pipeline)    14
2-2-2 使用貪婪演算法管線化(Greedy Algorithm)    16
2-3問題定義    18
第三章　周期時間限制下產生硬體最佳化的管線化結構方法    19
3-1周期時間限制下產生硬體最佳化的管線化結構流程    20
3-1-1 配線器轉型及管線化建表    21
3-1-2管線化線段計算    26
3-2 管線化區域路徑計算    27
3-3管線化插入及最佳化    28
第四章　實驗結果與討論    32
4-1 實驗環境    32
4-2 RC電路    32
4-3 共源放大器電路    33
4-4 串接式共源放大器    35
第五章　結論    37
第六章　參考文獻    38


                                

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