在系統層級以雙核心平台技術及組合語言最佳化實現MPEG AAC解碼器

簡易檢索 / 詳目顯示

回結果列表

研究生：	洪瑞鴻 Jui-hong Hung
論文名稱：	在系統層級以雙核心平台技術及組合語言最佳化實現MPEG AAC解碼器 System level design on MPEG AAC decoder with some scheduling and optimization
指導教授：	蔡宗漢 Tsung-han Tsai
口試委員:
學位類別：	碩士 Master
系所名稱：	資訊電機學院 - 電機工程學系 Department of Electrical Engineering
畢業學年度：	95
語文別：	中文
論文頁數：	67
中文關鍵詞：	組合語言、數位訊號處理器、音訊解碼器、先進式數位音訊解碼
外文關鍵詞：	DSP, Assembly Code, Audio Decoder, AAC
相關次數：	點閱：8 下載：0
分享至:	分享至facebook 分享至twitter

查詢本校圖書館目錄查詢臺灣博碩士論文知識加值系統勘誤回報

近年來通訊快速的發展，包括有線、無線、以及網路等等，對於多媒體的檔案，如影像、聲音、圖片等，都需要經過適當的壓縮及編解碼處理，才能夠在有限的頻寬上傳輸。在聲音的壓縮標準上，目前最為普遍使用的就是MPEG-1 Layer 3 (MP3)，然而隨著技術的進步，更高壓縮率及壓縮品質的音訊標準也不斷的被提出，在1994年Moving Picture Experts Group (MPEG) 所提出新一代的音訊壓縮標準MPEG-2 AAC，因為比MP3有更好的壓縮效率及壓縮品質，未來將有可能取代目前的MP3，而以MPEG-2 AAC為基本核心的MPEG-4 AAC也在1998年被提出，使用更多先進的技術來解決壓縮品質及壓縮效率的問題，MPEG-2/4 AAC也將成為繼MP3之後，下一個最廣為被應用的音訊壓縮標準。
目前大部分的音訊編解碼器包括MP3、AAC等都是利用數位訊號處理器(Digital Signal Processor，DSP)為主要的設計基礎，然而由於其複雜的演算法特性，一般設計者皆是從C語言的層次來進行系統的最佳化設計，但是因為無法真正與DSP的硬體架構一起做考量，通常在效能及功率上都會有所折扣。在本系統中將以組合語言的方式來實現MPEG AAC音訊解碼器，並以工研院自主研發之PAC DSP為開發平台，首先我們將從AAC演算法上進行初步的分析，提出快速的演算法達到初步的最佳化，然後配合PAC DSP的特殊硬體架構及指令集，以組合語言的方式做進一步的最佳化，最後實現一個完整MPEG-2/4 AAC音訊解碼器。

With the increased development of communications, including wire、wireless and network etc., all the multimedia files need compression to be transmitted on a limited bandwidth. In digital audio coding, MP3 is the most popular audio compression format in current days. However, with the progress of coding technology, new standards have been proposed which have higher efficiency and higher quality. MPEG-2 AAC, a new standard proposed by MPEG in 1994, has higher compression efficiency than MP3 and has chance to replace MP3 in the near future. MPEG-4 AAC, a newer standard proposed in 1998, which is based on the techniques used in MPEG-2 AAC but added some more efficient tools. Since the properties of higher compression rate and higher quality, MPEG-2/4 AAC will replace MP3 as the most popular audio compression standard.
Currently, most audio decoder including MP3, AAC are implemented based on the Digital Signal Processor (DSP). However, since the complex algorithms in audio standards, the designers can usually optimize the decoder in C-level. They cannot consider the DSP hardware architecture and algorithms simultaneously. Therefore, the decoding efficiency is decreased and power consumption is increased. In this project, we will implement the MPEG-2/4 AAC audio decoder on PAC DSP with assembly language. First, we will analyze the decoding algorithms and proposed fast algorithms for the initial optimization. Then, we write assembly for further optimization based on the PAC DSP’s architecture and instruction set. Finally, we will complete the optimized design of MPEG-2/4 AAC decoder.

Abstract.............................................I
誌謝.................................................II
目錄.................................................III
圖目.................................................V
表目.................................................IX
第一章 緒論..........................................1
1.1  音訊壓縮簡介.............................1
1.2  研究動機與目的...........................2
1.3  研究背景.................................2
第二章 AAC原理與編解碼流程及複雜度分析...............5
2.1  AAC原理..................................5
2.2  MPEG-2 AAC編碼流程.......................8
2.3  MPEG-2 AAC解碼流程.......................10
2.4  MPEG-4 AAC編解碼流程.....................13
2.5  AAC解碼器之複雜度分析....................16
第三章 Filterbank與TNS及快速演算法...................18
3.1  Filterbank and block switching...........18
3.2  IMDCT....................................18
3.3  Windowing and block switching............20
3.4  Temporal Noise Shaping...................24
3.5  Fast algorithm of IMDCT..................27
第四章 實現MPEG-2 AAC解碼器於Versatile platform......32
4.1  Introduction of Versatile................32
4.2  Hardware architecture of PAC DSP.........33
4.3  I/O definition of Filterbank.............35
4.4  I/O definition of TNS....................38
4.5  Dual core programming of Versatile.......39
4.6  Memory map and memory access of TNS、Filterbank...........................................42
4.7  Proposed assembly coding method of IMDCT................................................46
4.8  Implementation of Filterbank on PAC DSP..................................................48
第五章 PAC DSP模擬、除錯環境及實驗結果...............51
5.1  Coding flow of PAC DSP...................51
5.2  Assembler environment of PAC DSP.........52
5.3  Simulation environment of PAC DSP........53
5.4  Debug environment on Functional ISS......57
5.5  Debug environment on Versatile platform..59
5.6  Experimental results of TNS and Filterbank...........................................62
第六章 結論..........................................65
參考文獻.............................................66

                                

[1] ISO/IEC 13818-7, “Information Technology – Generic coding of moving picture and associated audio, Part 7: Advanced Audio Coding,” Apr. 1997.
[2] ISO/IEC 14496-3, “Information Technology – Very low bitrate audio-visual coding, Part 3: Audio,” May 1998.
[3] ISO/IEC 11172-3, “Information Technology – Coding of moving pictures and associated audio for digital storage media at up to 1.5 Mbit/s, Part3: Audio,” Aug. 1993.
[4] Matthew A. Watson and Peter Buettner, “Design and implementation of AAC decoders,” IEEE Transactions on Consumer Electronics, Vol. 46, Issue: 3, pp.819-824, Aug. 2000.
[5] Jing Chen and Heng-Ming Tai, “MPEG-2 AAC decoder on a fixed-point DSP,” IEEE Transactions on Consumer Electronics, Vol. 45, Issue: 4, pp.1200-1205, Nov. 1999.
[6] Vladimir Mesarovic, N. D. Hemkumr and Miroslav Dokic, “MPEG-4 AAC audio decoding on a 24-bit fixed-point dual-DSP architecture,” IEEE International Symposium on Circuits and Systems (ISCAS), Vol. 3, pp.706-709, May 2000.
[7] Kyoung Ho Bang, Joon Seok Kim, Nam Hun Jeong, Young Cheol Park and Dae Hee Youn, “Design optimization of MPEG-2 AAC decoder,” IEEE Transactions on Consumer Electronics, Vol. 47, Issue: 4, pp.895-903, Nov. 2001.
[8] Jing Chen and Heng-Ming Tai, “MPEG-2 AAC decoder on a fixed-point DSP,” IEEE Transactions on Consumer Electronics, Vol. 45 Issue: 4, pp.1200-1205, Nov. 1999.
[9] Keun-Sup Lee, Young Cheol Park and Dae Hee Youn, “Software optimization of the MPEG-audio decoder using a 32-bit MCU RISC processor,” IEEE Transactions on Consumer Electronics, Vol. 48, Issue: 3, pp.671-676, Aug. 2002.
[10] Yuichiro Takamizawa, Kouhei Nadehara, Max Boegli, Masao Ikekawa and Ichiro Kuroda, “MPEG-2 AAC 5.1-channel decoder software for a low-power embedded RISC microprocessor,” IEEE Workshop on Signal Processing Systems (SIPS), pp.351-360, Oct. 1999.
[11] Pi-Chung Wang, Yuan-Rung Yang, Chun-Liang Lee and Hung-Yi Chang, “A memory-efficient Huffman decoding algorithm,” International Conference on Advanced Information Networking and Applications, Vol. 2, pp. 475-479, Mar. 2005.
[12] Bai-Jue Shieh, Yew-San Lee and Chen-Yi Lee, “A high-throughput memory-based VLC decoder with codeword boundary prediction,” IEEE Transactions on Circuits and Systems for Video Technology, Vol. 10, Issue: 8, pp.1514-1521, Dec. 2000.
[13] Reza Hashemian, “Design and hardware implementation of a memory efficient Huffman decoding,” IEEE Transactions on Consumer Electronics, Vol. 40, Issue: 3, pp.345-352, Aug. 1994.
[14] Shaw-Min Lei and Ming-Ting Sun, “An entropy coding system for digital HDTV applications,” IEEE Transaction on Circuits and System for Video Technology, Vol. 1, Issue: 1, pp.147-155, Mar. 1991.
[15] Keun-Sup Lee, Nam-Hun Jeong, Kyoung-Ho Bang and Dae-Hee Youn, “A VLSI implementation of MPEG-2 AAC decoder system,” The First IEEE Asia Pacific Conference on ASICs, pp.139-142, Aug. 1999.
[16] Tsung-Han Tsai, Wen-Cheng Chen and Chun-Nan Liu “A low power VLSI implementation for variable length decoder in MPEG-1 layer III”, IEEE International Conference on Multimedia & Expo (ICME), Vol. 1, pp.133-136, July 2003.
[17] Tsung-Han Tsai and Chuh-Chu Yen, “A high quality re-quantization/quantization method for MP3 and MPEG-4 AAC audio coding,” IEEE International Symposium on Circuits and Systems, Vol. 3, pp.851-854, May 2002.
[18] P. Duhamel, Y. Mahieux and J.P. Petit, “A fast algorithm for the implementation of filter banks based on `time domain aliasing cancellation'',” International Conference on Acoustics, Speech, and Signal Processing, Vol. 3, pp.2209-2212, Apr. 1991.
[19] PAC DSP v3.0 Software Developer’s Bible-vol.2 Instruction Set Manual.
[20] PAC DSP v3.0 Software Developer’s Bible-vol.3 Programming Constraints and Optimization Guide.
[21] PAC DSP v3.0 Functional Instruction Set Simulator User Guide.
[22] Chang Won Ryu, Dong Hun Lee, Hua Jun Ch, Kyoung Su Kwan, Tae Hoon Kim and Ju Sung Park, ”Design of Digital Audio DSP Core,” International forum on Strategic technology, pp.59-62, Oct. 2006.
[23] Keun-Sup Lee, Nam-Hun Jeong, Kyoung-Ho Bang and Dae-Hee Youn, “A VLSI implementation of MPEG-2 AAC decoder system,” The first IEEE Asia Pacific Conference on ASICs, pp139-142, Aug. 1999.
[24] Kyoung Ho Bang, Nam Hun Jeong, Joon Seok Kim, Young Cheol Park, Dae Hee Youn, “Design and VLSI implementation of a digital audio-specific DSP core for MP3/AAC,” International Conference on Consumer Electronics, pp220-221, June. 2002.

簡易檢索 / 詳目顯示

相關論文