通用LIB格式運用於尺寸可變的嵌入式記憶體功率模型

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研究生：	游智嘉 Chi-Chia Yu
論文名稱：	通用LIB格式運用於尺寸可變的嵌入式記憶體功率模型 A Scalable Power Modeling Approach for Embedded Memory Using LIB Format
指導教授：	劉建男 Chien-Nan Liu
口試委員:
學位類別：	碩士 Master
系所名稱：	資訊電機學院 - 電機工程學系 Department of Electrical Engineering
畢業學年度：	94
語文別：	英文
論文頁數：	51
中文關鍵詞：	記憶體、功率
外文關鍵詞：	memory, power
相關次數：	點閱：14 下載：0
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摘要
在這篇論文裡，我們發展兩種方法改進記憶功率估計的準確。我們提升的記憶體功率模型能不僅考慮記憶體的操作模式，也考慮輸入位址切換的影響和從記憶體架構中得到不同大小記憶體之間的比例因子。我們提出的方法可以有效的結合記憶體產生器產生任意大小的記憶體功率模型，無需再對不同大小的記憶體再做一次功率模型。接著提出來的Dummy Modular方法可以將我們的功率模型和商業估測功率軟體流程互相結合。實驗結果已經顯示我們的記憶功率模型的平均誤差少於5%。

Abstract
In this work, we develop two methods to improve the accuracy of memory power estimation. Our enhanced memory power model can consider not only the operation mode of memory access, but also the address switching effect and the scaling factors that use the information of physical architecture. The proposed approach is very useful to be combined with memory compiler to generate accurate power model for any specified memory size without extra characterization costs. Then the proposed dummy modular approach can link our enhanced memory power model into commercial power estimation flow smoothly. The experimental results have shown that the average error of our memory power model is only less than 5%.

CONTENTS
Chapter 1  Introduction	1
Chapter 2  Preliminary	5
2.1       Power Consumption of CMOS Digital circuit	5
2.2       Traditional Memory Power Estimation	7
2.3       Embedded Memory Architecture	11
2.4       Linear Regression	14
2.4.1    Linear Regression	14
2.4.2    Least-Squares Regression	15
2.4.3    Correlation	15
Chapter 3  Enhanced Memory Power Modeling Using LIB Format	17
3.1       Dummy Modular Approach	19
3.2       Combine Our Model with Memory Compiler in Current EDA Flow	22
Chapter 4   Scalable Model Equations	23
4.1       Memory Core	27
4.2       Controller Circuit	28
4.3       Column/Row Decoder	29
4.4       Scalable Methodology	30
4.5       Frequency and Leakage Power	32
4.5.1    Leakage Power	32
4.5.2    Frequency	33
Chapter 5   Experimental Results	35
Chapter 6   Conclusions	41
References                 42

                                

References
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[2] “Library Compiler User Guide: Modeling Timing and Power Technology Libraries”, Synopsys, March 2003.
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[4] Amrutur, B.S.; Horowitz, M.A., “Speed and power scaling of SRAM''s”, IEEE Trans. Solid-State Circuits, vol. 35, Feb. 2000 pp. 175 – 185.
[5] Evans, R.J.; Franzon, P.D., “Energy consumption modeling and optimization for SRAM''s”, IEEE Trans. Solid-State Circuits, vol. 30, May 1995, pp. 571 – 579.
[6] Chinosi, M.; Zafalon, R.; Guardiani, C., “Automatic characterization and modeling of power consumption in static RAMs”, Low Power Electronics and Design, Aug. 1998.
[7] Coumeri, S.L.; Thomas, D.E., Jr., “Memory modeling for system synthesis”, IEEE Trans. On VLSI Syst., vol. 8, June 2000, pp. 327 – 334.
[8] Schmidt, E.; von Colln, G.; Kruse, L.; Theeuwen, F.; Nebel, W., “Memory Power Models for Multilevel Power Estimation and Optimization”, IEEE Trans. VLSI Syst., vol. 10, April 2002, pp. 106-109.
[9] J. Olson, I. Nedelchev, Y. Lin, A. Mauskar, and J. Sproch, “STATE DEPENDENT POWER MODELING,” US Patent # 5,838,579, 1998.
[10] “TSMC 0.25μm Process SRAM-SP-HD Generator User Manual”, Release 5.0, Artisan Comp., January 2002.
[11] Ashok K. Sharma, “Advanced Semiconductor Memories: Architectures, Designs, and Applications”, Piscataway, NJ: IEEE Press; Hoboken, NJ: Wiley-Interscience, 2003.
[12] Wen-Tsan Hsieh; Chien-Nan Jimmy Liu; Yao-Feng Wang; Yi-Fang Chiu; “An efficient power modeling approach for embedded memory using LIB format”, VLSI Design, Automation and Test, 2005. (VLSI-TSA-DAT). 2005 IEEE VLSI-TSA International Symposium on 27-29 April 2005 Page(s):55 – 58

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