| 研究生: |
謝承軒 Cheng-hsuan Hsieh |
|---|---|
| 論文名稱: |
氧化鋁/砷化銦鰭式場效電晶體之製作與特性分析 Fabrication and Characterization of Al2O3/InAs Fin Field-Effect Transistors |
| 指導教授: |
綦振瀛
Jen-inn Chyi |
| 口試委員: | |
| 學位類別: |
碩士 Master |
| 系所名稱: |
資訊電機學院 - 電機工程學系 Department of Electrical Engineering |
| 論文出版年: | 2014 |
| 畢業學年度: | 102 |
| 語文別: | 中文 |
| 論文頁數: | 90 |
| 中文關鍵詞: | 砷化銦 、氧化鋁 、金屬氧化物半導體電容 、鰭式場效電晶體 |
| 外文關鍵詞: | InAs, Al2O3, MOSCAP, FinFET |
| 相關次數: | 點閱:12 下載:0 |
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砷化銦化合物半導體因其具備低能隙、高電子遷移率與高電子飽和速度,被視為低耗能電晶體的通道層材料選項之一,此三-五族材料的鰭狀電晶體架構,在未來有相當高的機會被應用在積體電路中。然而,目前高介電常數材料與三-五族半導體間的界面缺陷多寡是影響元件特性最關鍵的問題,因此,本論文中將提出適當地砷化銦表面處理方式,開發奈米級砷化銦鰭式場效電晶體,並探討其元件特性。
本研究是以原子層沉積法成長的氧化鋁作為高介電常數材料,並於成長前藉由不同化學溶液對砷化銦的表面進行處理,同時搭配金屬沉積後的退火處理,修復氧化鋁與氧化鋁/砷化銦界面缺陷,最終提出一個合適的表面清理與熱退火處理方式,有效降低氧化鋁/砷化銦界面缺陷密度和氧化層缺陷密度。
製作鰭式場效電晶體所使用之試片是以分子束磊晶法所成長,以砷化鎵為基板,銻化物為緩衝層及砷化銦為通道層。鰭式場效電晶體的製程技術開發包括:以電子束微影系統進行鰭式通道、歐姆接觸與閘極區域的定義,過程包含微影劑量、光阻形貌與金屬沉積後的形貌開發,同時引入BCB平坦化製程,解決奈米級元件的接觸窗口不易形成的問題。最後,本研究成功利用電子束微影技術開發出閘極長度為0.5 μm、源極至汲極距離為2 μm與有效鰭式通道寬度為60 nm之砷化銦表面通道鰭式場效電晶體。其元件之最大汲極電流密度為119 μA/μm,最大轉導值為77.2 μS/μm,臨界電壓為-2.37 V,汲極電流開關比為136以及次臨界擺幅為524 mV/decade。
Because of its narrow band gap, high electron mobility and high electron saturation velocity, InAs is considered a promising candidate for low power consumption field-effect transistors (FETs). Its fin field-effect transistors (FinFETs) might be used in the integrated circuits in the future. However, the interface traps at high-κ/III-V interface, which have significant negative influence on device performance, must be reduced before it can be used for practical applications. In this work, methods of surface treatment for InAs are studied. Nano-scale InAs FinFETs are also demonstrated and characterized.
Al2O3 prepared by atomic layer deposition is used as the high-κ material in this study. Before the deposition, various chemical treatments on InAs surface and post metallization annealed are investigated. A proper treatment is proposed to minimize the interface trap density and oxide trap density.
The InAs surface channel epi-wafers are grown on GaAs substrates with an Sb-based buffer layer by molecular beam epitaxy. The channel width, ohmic area and gate profile of the FinFETs are defined by electron-beam lithography. The effects of electron beam dosage on photoresist profile and metal profile are examined in this study. Benzocyclobutene planarization process is also employed in this nano-scale device. Al2O3/InAs FinFETs with a gate length of 0.5 μm, source to drain separation of 2 μm and fin width of 60 nm are successfully fabricated. A maximum drain current of 119 μA/μm, a maximum transconductance of 77.2 μS/μm, a threshold voltage of -2.37 V, a drain current on-off ratio of 136 and a sub-threshold swing of 524 mV/decade are obtained.
[1] A. Ali, H. Madan, A. Agrawal, I. Ramirez, R. Misra, J. B. Boos, B. R. Bennett, J. Lindemuth, and S. Datta, “Enhancement-Mode Antimonide Quantum-Well MOSFETs With High Electron Mobility and Gigahertz Small-Signal Switching Performance,” IEEE Electron Device Letters, vol. 32, no. 12, pp. 1689-1691, 2011.
[2] M. Bohr, “The evolution of scaling from the homogeneous era to the heterogeneous era,” IEEE International Electron Devices Meeting, pp. 1.1.1-1.1.6, 2011.
[3] K. Mistry, C. Allen, C. Auth, B. Beattie, D. Bergstrom, M. Bost, M. Brazier, M. Buehler, A. Cappellani, R. Chau, C. H. Choi, G. Ding, K. Fischer, T. Ghani, R. Grover, W. Han, D. Hanken, M. Hattendorf, J. He, J. Hicks, R. Huessner, D. Ingerly, P. Jain, R. James, L. Jong, S. Joshi, C. Kenyon, K. Kuhn, K. Lee, H. Liu, J. Maiz, B. McIntyre, P. Moon, J. Neirynck, S. Pae, C. Parker, D. Parsons, C. Prasad, L. Pipes, M. Prince, P. Ranade, T. Reynolds, J. Sandford, L. Shifren, J. Sebastian, J. Seiple, D. Simon, S. Sivakumar, P. Smith, C. Thomas, T. Troeger, P. Vandervoorn, S. Williams, and K. Zawadzki, “A 45nm Logic Technology with High-k+Metal Gate Transistors, Strained Silicon, 9 Cu Interconnect Layers, 193nm Dry Patterning, and 100% Pb-free Packaging,” IEEE International Electron Devices Meeting, pp. 247-250, 2007.
[4] A. J. Strojwas, “Is the bulk vs. SOI battle over?,” International Symposium on VLSI Technology, Systems, and Applications, pp. 1-2, 2013.
[5] T. I. Tsai, T. S. Chao, C. J. Su, H. C. Lin, T. Y. Huang, H. C. Lin, and Y. J. Wei, “Low temperature polycrystalline Si nanowire devices with gate-all-around Al2O3/TiN structure using an implant-free technique,” IEEE 4th International Nanoelectronics Conference, pp. 1-2, 2011.
[6] R. Tsai, M. Barsky, J. B. Boos, B. R. Bennett, J. Lee, N. A. Papanicolaou, R. Magno, C. Namba, P. H. Liu, D. Park, R. Grundbacher, and A. Gutierrez, “Metamorphic AlSb/InAs HEMT for low-power, high-speed electronics,” Proc. IEEE GaAs Dig, pp. 294-297, 2003.
[7] M. L. A. J. Bauer, “III-V material : latest developments and perspectives,” 2008.
[8] D. K. Schroder, “Semiconductor Material and Device Characterization,” 2006.
[9] D. Y. Petrovykh, M. J. Yang, and L. J. Whitman, “Chemical and electronic properties of sulfur-passivated InAs surfaces,” Surface Science, vol. 523, no. 3, pp. 231-240, 2003.
[10] M. Milojevic, C. L. Hinkle, F. S. Aguirre-Tostado, H. C. Kim, E. M. Vogel, J. Kim, and R. M. Wallace, “Half-cycle atomic layer deposition reaction studies of Al2O3 on (NH4)2S passivated GaAs(100) surfaces,” Applied Physics Letters, vol. 93, no. 25, pp. 252905, 2008.
[11] N. Eassa, D. M. Murape, J. H. Neethling, R. Betz, E. Coetsee, H. C. Swart, A. Venter, and J. R. Botha, “Chalcogen based treatment of InAs with [(NH4)2S/(NH4)2SO4],” Surface Science, vol. 605, no. 11-12, pp. 994-999, 2011.
[12] E. O’Connor, B. Brennan, V. Djara, K. Cherkaoui, S. Monaghan, S. B. Newcomb, R. Contreras, M. Milojevic, G. Hughes, M. E. Pemble, R. M. Wallace, and P. K. Hurley, “A systematic study of (NH4)2S passivation (22%, 10%, 5%, or 1%) on the interface properties of the Al2O3/In0.53Ga0.47As/InP system for n-type and p-type In0.53Ga0.47As epitaxial layers,” Journal of Applied Physics, vol. 109, no. 2, pp. 024101, 2011.
[13] S. A. Jewett, and A. Ivanisevic, “Wet-chemical passivation of InAs: toward surfaces with high stability and low toxicity,” Acc Chem Res, vol. 45, no. 9, pp. 1451-9, Sep 18, 2012.
[14] D. Wheeler, L. E. Wernersson, L. Fröberg, C. Thelander, A. Mikkelsen, K. J. Weststrate, A. Sonnet, E. M. Vogel, and A. Seabaugh, “Deposition of HfO2 on InAs by atomic-layer deposition,” Microelectronic Engineering, vol. 86, no. 7-9, pp. 1561-1563, 2009.
[15] H.-D. Trinh, E. Y. Chang, Y.-Y. Wong, C.-C. Yu, C.-Y. Chang, Y.-C. Lin, H.-Q. Nguyen, and B.-T. Tran, “Effects of Wet Chemical and Trimethyl Aluminum Treatments on the Interface Properties in Atomic Layer Deposition of Al2O3 on InAs,” Japanese Journal of Applied Physics, vol. 49, no. 11, pp. 111201, 2010.
[16] C. A. Lin, M. L. Huang, P. C. Chiu, H. K. Lin, J. I. Chyi, T. H. Chiang, W. C. Lee, Y. C. Chang, Y. H. Chang, G. J. Brown, J. Kwo, and M. Hong, “InAs MOS devices passivated with molecular beam epitaxy-grown Gd2O3 dielectrics,” Journal of Vacuum Science & Technology B: Microelectronics and Nanometer Structures, vol. 30, no. 2, pp. 02B118, 2012.
[17] H.-D. Trinh, Y.-C. Lin, H.-C. Wang, C.-H. Chang, K. Kakushima, H. Iwai, T. Kawanago, Y.-G. Lin, C.-M. Chen, Y.-Y. Wong, G.-N. Huang, M. Hudait, and E. Y. Chang, “Effect of Postdeposition Annealing Temperatures on Electrical Characteristics of Molecular-Beam-Deposited HfO2 on n-InAs/InGaAs Metal-Oxide-Semiconductor Capacitors,” Applied Physics Express, vol. 5, no. 2, pp. 021104, 2012.
[18] Q.-H. Luc, E. Y. Chang, H.-D. Trinh, H.-Q. Nguyen, B.-T. Tran, and Y.-C. Lin, “Effect of annealing processes on the electrical properties of the atomic layer deposition Al2O3/In0.53Ga0.47As metal oxide semiconductor capacitors,” Japanese Journal of Applied Physics, vol. 53, no. 4S, pp. 04EF04, 2014.
[19] L. B. Ruppalt, E. R. Cleveland, J. G. Champlain, S. M. Prokes, J. Brad Boos, D. Park, and B. R. Bennett, “Atomic layer deposition of Al2O3 on GaSb using in situ hydrogen plasma exposure,” Applied Physics Letters, vol. 101, no. 23, pp. 231601, 2012.
[20] C. H. Wang, S. W. Wang, G. Doornbos, G. Astromskas, K. Bhuwalka, R. Contreras-Guerrero, M. Edirisooriya, J. S. Rojas-Ramirez, G. Vellianitis, R. Oxland, M. C. Holland, C. H. Hsieh, P. Ramvall, E. Lind, W. C. Hsu, L. E. Wernersson, R. Droopad, M. Passlack, and C. H. Diaz, “InAs hole inversion and bandgap interface state density of 2 × 1011 cm−2 eV−1 at HfO2/InAs interfaces,” Applied Physics Letters, vol. 103, no. 14, pp. 143510, 2013.
[21] Cheng-Hsuan Hsieh, Jei-Wei Hsu, Pei-Chin Chiu, Wei-Jen Hsueh, Nien-Tze Yeh and Jen-Inn Chyi, “Low Interface Trap Density HfO2/n-InAs MOS Capacitors Prepared by In-situ Atomic Layer Deposition,” International Electron Devices and Materials Symposium, Taipei, Nantou, R.O.C., 2013.
[22] 許哲瑋, “氧化鉿/砷化銦金氧半結構之製備及其界面與電性研究, 國立中央大學碩士論文, 2012.
[23] J. Wu, E. Lind, R. Timm, M. Hjort, A. Mikkelsen, and L. E. Wernersson, “Al2O3/InAs metal-oxide-semiconductor capacitors on (100) and (111)B substrates,” Applied Physics Letters, vol. 100, no. 13, pp. 132905, 2012.
[24] H. D. Trinh, G. Brammertz, E. Y. Chang, C. I. Kuo, C. Y. Lu, Y. C. Lin, H. Q. Nguyen, Y. Y. Wong, B. T. Tran, K. Tran, and H. Tran, “Electrical Characterization of Al2O3/n-InAs Metal-Oxide-Semiconductor Capacitors With Various Surface Treatments,” IEEE Electron Device Letters, vol. 32, no. 6, pp. 752-754, 2011.
[25] Y. Q. Wu, R. S. Wang, T. Shen, J. J. Gu, and P. D. Ye, “First experimental demonstration of 100 nm inversion-mode InGaAs FinFET through damage-free sidewall etching,” IEEE International Electron Devices Meeting, pp. 1-4, 2009.
[26] S. H. Kim, M. Yokoyama, R. Nakane, O. Ichikawa, T. Osada, M. Hata, M. Takenaka, and S. Takagi, “High performance sub-20-nm-channel-length extremely-thin body InAs-on-insulator tri-gate MOSFETs with high short channel effect immunity and Vth tunability,” IEEE International Electron Devices Meeting, pp. 16.4.1-16.4.4, 2013.
[27] R. Engel-Herbert, Y. Hwang, and S. Stemmer, “Comparison of methods to quantify interface trap densities at dielectric/III-V semiconductor interfaces,” Journal of Applied Physics, vol. 108, no. 12, pp. 124101, 2010.
[28] H.-Y. Lin, S.-L. Wu, C.-C. Cheng, C.-H. Ko, C. H. Wann, Y.-R. Lin, S.-J. Chang, and T.-B. Wu, “Influences of surface reconstruction on the atomic-layer-deposited HfO2/Al2O3/n-InAs metal-oxide-semiconductor capacitors,” Applied Physics Letters, vol. 98, no. 12, pp. 123509, 2011.
[29] Y. Hwang, R. Engel-Herbert, N. G. Rudawski, and S. Stemmer, “Analysis of trap state densities at HfO2/In0.53Ga0.47As interfaces,” Applied Physics Letters, vol. 96, no. 10, pp. 102910, 2010.
[30] G. Miceli, and A. Pasquarello, “Defect levels at GaAs/Al2O3 interfaces: As–As dimer vs. Ga dangling bond,” Applied Surface Science, vol. 291, no. 12, pp. 16-19, 2014.
[31] E. J. Kim, L. Wang, P. M. Asbeck, K. C. Saraswat, and P. C. McIntyre, “Border traps in Al2O3/In0.53Ga0.47As (100) gate stacks and their passivation by hydrogen anneals,” Applied Physics Letters, vol. 96, no. 1, pp. 012906, 2010.
[32] R. Timm, A. Fian, M. Hjort, C. Thelander, E. Lind, J. N. Andersen, L. E. Wernersson, and A. Mikkelsen, “Reduction of native oxides on InAs by atomic layer deposited Al2O3 and HfO2,” Applied Physics Letters, vol. 97, no. 13, pp. 132904, 2010.
[33] Y. Yuan, L. Wang, B. Yu, B. Shin, J. Ahn, P. C. McIntyre, P. M. Asbeck, M. J. W. Rodwell, and Y. Taur, “A Distributed Model for Border Traps in Al2O3-InGaAs MOS Devices,” IEEE Electron Device Letters, vol. 32, no. 4, pp. 485-487, 2011.
[34] 洪聖宗, “電子束微影鄰近效應修正與BA-m Benzoxazine film 製備抗反射層,”國立中央大學碩士論文, 2006.
[35] 王聖瑜, “次微米銻砷化銦鎵基極雙異質接面雙極性電晶體製程技術發展與特性分析,”國立中央大學博士論文, 2013.
[36] S. Mathew, L. K. Bera, N. Balasubramanian, M. S. Joo, and B. J. Cho, “Channel mobility degradation and charge trapping in high-k/metal gate NMOSFETs,” Thin Solid Films, vol. 462-463, pp. 11-14, 2004.
[37] W. Zhu, J. P. Han, and T. P. Ma, “Mobility Measurement and Degradation Mechanisms of MOSFETs Made With Ultrathin High-k Dielectrics,” IEEE Transactions on Electron Devices, vol. 51, no. 1, pp. 98-105, 2004.
[38] F. Wang, S. Yip, N. Han, K. Fok, H. Lin, J. J. Hou, G. Dong, T. Hung, K. S. Chan, and J. C. Ho, “Surface roughness induced electron mobility degradation in InAs nanowires,” Nanotechnology, vol. 24, no. 37, pp. 375202, Sep 20, 2013.
[39] C. H. Lee, T. Nishimura, T. Tabata, C. Lu, W. F. Zhang, K. Nagashio, and A. Toriumi, “Reconsideration of electron mobility in Ge n-MOSFETs from Ge substrate side- Atomically flat surface formation, layer-by-layer oxidation, and dissolved oxygen extraction,” IEEE International Electron Devices Meeting, pp. 2.3.1-2.3.4, 2013.