| 研究生: |
許景銘 Hsu, Jing-Ming |
|---|---|
| 論文名稱: |
以軟體定義無線電實現DVB-T基頻接收機 Implementation of DVB-T Baseband Receiver with a SDR platform |
| 指導教授: |
陳逸民
Yih-Ming Chen |
| 口試委員: | |
| 學位類別: |
碩士 Master |
| 系所名稱: |
資訊電機學院 - 通訊工程學系 Department of Communication Engineering |
| 論文出版年: | 2016 |
| 畢業學年度: | 105 |
| 語文別: | 中文 |
| 論文頁數: | 87 |
| 中文關鍵詞: | 數位電視廣播 、時間同步 、頻率同步 、軟體定義無線電 |
| 外文關鍵詞: | DVB-T, Time Synchronization, Frequency Synchronization, Software-defined Radio |
| 相關次數: | 點閱:9 下載:0 |
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台灣採用歐洲廣播聯盟(European Broadcast Union, EBU)所制訂的數位電視廣播(Digital Video Broadcasting, DVB)規格,在本論文中,將以實務軟體定義無線電(Software-defined Radio,SDR)實現DVB-T接收機。
實驗室結合FPGA板(A7)及射頻模組(AD9361)完成軟體定義無線電平台,並設計硬體進行DVB-T訊號解調,此接收機所需用到數位訊號處理模組包含降頻取樣、時間同步、頻率同步、快速傅立葉轉換、解訊框架構、通道估測器、通道等化器。先實錄訊號以MATLAB訊號解調,再選取相對應之硬體規格參數撰寫硬體描述語言,並用ModelSim模擬電路時序後,再以軟體無線電平台實錄訊號並驗證其硬體功能。便可用實務軟體定義無線電DVB-T基頻接收機於各地量測訊號並分析。
Digital Video Broadcasting - Terrestrial is a digital video broadcast standard adopted in Taiwan, and it is ratifies by European Broadcast Union. In this thesis, we implement the DVB-T Baseband Receiver with a Realistic Software-defined Radio platform.
Our laboratory combine FPGA and Radio Frequency module(AD9361) to finish SDR platform. This baseband receiver need the digital signal processing units which are down sampling, time synchronizer, frequency synchronizer, Fast Fourier Transform processor, channel estimator, channel equlizer. First, recording DVB-T signal is programmed using MATLAB to demodulate the signal. Second, the specification for each digital signal processing units is designed, progrmaed by using Verilog hardware description language and verified with ModelSim. Then, the real-time haradware is implemented and verified with SDR platform. The measurement and analysis of recording signal in the difference places by DVB-T Baseband Receiver with a Realistic Software-defined Radio platform.
[1]“Etsi en 300 744 v1.6.1 digital video broadcasting (dvb),” Digital Video Broad- casting (DVB);Framing structure, channel coding and modulation for digital terrestrial television, 2009.
[2]T. L. Chen, “Design and fpga implementation of baseband transmitter for dvb-t system,” National Central University, Master’s thesis, 2014.
[3]M. Y. Hsu, “Design and fpga implementation of baseband receiver for dvb-t system,” National Central University, Master’s thesis, 2011.
[4]I. Tsai, “Design and fpga implementation of sampling frequency offset synchro- nization for dvb-t receiver in baseband,” National Central University, Master’s thesis, 2011.
[5]T.-a. Chao, “Design and implementation of digital front-end and synchroniza- tion system for dvb-t receiver,” National Central University, Master’s thesis, 2006.
[6]J. W. Cooley and J. W. Tukey, “An algorithm for the machine calculation of complex fourier series,” Mathematics of computation, vol. 19, no. 90, pp. 297– 301, 1965.
[7]R. Andraka, “A survey of cordic algorithms for fpga based computers,” in Pro- ceedings of the 1998 ACM/SIGDA sixth international symposium on Field pro- grammable gate arrays, pp. 191–200, ACM, 1998.
[8]J. Song, Z. Yang, L. Yang, K. Gong, C. Pan, J. Wang, and Y. Wu, “Tech- nical review on chinese digital terrestrial television broadcasting standard and measurements on some working modes,” IEEE Transactions on Broadcasting, vol. 53, no. 1, pp. 1–7, 2007.
[9]S. He and M. Torkelson, “Designing pipeline fft processor for ofdm (de) mod- ulation,” in Signals, Systems, and Electronics, 1998. ISSSE 98. 1998 URSI International Symposium on, pp. 257–262, IEEE, 1998.
[10]Y.-M. Chen and I.-Y. Kuo, “Design of lowpass filter for digital down converter in ofdm receivers,” in 2005 International Conference on Wireless Networks, Communications and Mobile Computing, vol. 2, pp. 1094–1099, IEEE, 2005.
[11]S.-H. Chen, W.-H. He, H.-S. Chen, and Y. Lee, “Mode detection, synchroniza- tion, and channel estimation for dvb-t ofdm receiver,” in Global Telecommuni- cations Conference, 2003. GLOBECOM’03. IEEE, vol. 5, pp. 2416–2420, IEEE, 2003.
[12]S. He and M. Torkelson, “A new approach to pipeline fft processor,” in Parallel Processing Symposium, 1996., Proceedings of IPPS’96, The 10th International, pp. 766–770, IEEE, 1996.