本論文主要提出利用閘極掘入的方式搭配MIS結構來製作出增強型(Enhancement-mode)操作之氮化鋁鎵/氮化鎵場效功率電晶體，利用高密度偶和電漿蝕刻系統（Inductively Coupled Plasma Etching System，ICP）通入BCl3/Cl2/Ar/O2 (19/50/5/6 sccm)四種氣體來蝕刻閘極區域，可有效降低蝕刻速率以及表面粗糙度。此外，相較於其他閘極氧化層材料，利用原子沉積系統 (Atomic layer deposited, ALD)成長高介電係數和寬能隙之氧化鋁來當作閘極介電層，可有效降低閘極漏電流及提升轉導率。單顆電晶體元件部分，我們設計閘極長度為2 μm之指叉型閘極和環狀閘極兩種做比較，順偏特性部份環形閘極可以達到190 mA/mm的電流密度以及76.3 mS/mm的轉導率較指叉型閘極的150 mA/mm電流密度和45 mS/mm的轉導率優異，由Id-Vd曲線圖之斜率求得環型閘極之開啟電阻為(7.53 mΩ-cm2)亦較指叉型閘極(的8.21 mΩ-cm2要小)，兩種增強型元件之臨限電壓分別為1.5 V及1 V。在元件的逆偏特性部份，環型閘極元件在Vg為0 V下之閘極漏電流比指叉型小了兩個數量級。閘極-源極之氧化層耐壓可以達到12 V，單顆元件之崩潰電壓最高可以達到118 V。
為了要實現功率元件之大電流特性，我們設計了多指叉並聯之場效功率電晶體，其中40根並聯之指叉型閘極元件可以達到0.386 A之大電流及1.8 V常關型操作，40根並聯之環形閘極元件可以達到0.44 A之大電流及1.3 V常關型操作。此外我們從線阻和針阻的量測中發現針阻和線阻就占了全部阻抗的2/3，這表示實際注入之電流比預期小了1/3，導致實際電流不如預期，如果要提升電流大小可以使用金屬打線(Wire bonding)的方式解決。
此外，藉由分析不同缺陷存在於GaN MOS電容在不同偏壓下之能帶彎曲情形，讓我們成功分析出缺陷能階對於臨限電壓之影響，此外我們也分析出當類受體的介面缺陷能態(Acceptor like state)過多時，在閘極介面處會有漏電流路徑存在，因此對於閘極掘入式MOSFET來說，降低介面缺陷能態是很重要的。

Enhancement mode AlGaN/GaN MOSFETs fabricated by gate recessed technique and MIS structure is mentioned in this study. ICP dry etch the gate recessed area with BCl3/Cl2/Ar/O2 (19/50/5/6 sccm) gas can effective reduce the etching rate and surface roughness. Furthermore, Compare with other gate dielectric material the Al2O3 gate dielectric grew by ALD (Atomic Layer Deposited) with high k and wide band gap can reduce the gate leakage and improve transconductance. According to the electrical property of 2μm L¬g single device, we design finger type device compare with circular device. Circular type device can achieve 190 mA/mm current density and 76.3 mS/mm transconductance is better than finger type device with 150 mA/mm current density and 45 mS/mm transconductance. From the slope of Id-Vd curve, we can estimate the on resistance of two devices. The on resistance of circular type device (7.53 mΩ-cm2) is lower than finger type device (8.21 mΩ-cm2). The threshold voltage of two different kinds of device are 1.5V and 1V. According to the I-V characteristic in off state, the gate leakage current of Circular type device is two orders lower than finger type device. The oxide breakdown is about 12V and the maximum breakdown of single device is 118 V.
In order to realize high current property of power device, we design multi-finger device to achieve. Forty finger type device can achieve 0.38 A high current and 1.8V threshold voltage, forty circular type device can achieve 0.44 A high current and 1.3 V threshold voltage. In addition, we find that two-thirds of total resistance is probe resistance and bus line resistance. This indicate that the real injected current is lower than our expectation. We can use wire bonding method to improve the current property of the 40 finger device.
By analyzing the band diagram of GaN MOS capacitance with different bias and trap state, we can find the relationship between interface state and threshold voltage. Furthermore, we also find that more acceptor type interface state will cause leakage current path in gate interface. So, it is important to reduce the interface state in Gate recessed MOSFETs.

[1] T. Palacios, A. Chakraborty, S. Rajan, C. Poblenz, S. Keller, S. P. DenBaars, J. S. Speck, and U. K. Mishra, "High-power AlGaN/GaN HEMTs for Ka-band applications," IEEE Electron Device Letters, vol. 26, pp. 781-783, 2005.
[2] O. Ambacher, B. Foutz, J. Smart, J. R. Shealy, N. G. Weimann, K. Chu, M. Murphy, A. J. Sierakowski, W. J. Schaff, L. F. Eastman, R. Dimitrov, A. Mitchell, and M. Stutzmann, "Two dimensional electron gases induced by spontaneous and piezoelectric polarization in undoped and doped AlGaN/GaN heterostructures," Journal of Applied Physics, vol. 87, p. 334, 2000.
[3] M. A. Khan, X. Hu, G. Sumin, A. Lunev, J. Yang, R. Gaska, and M. S. Shur, "AlGaN/GaN metal oxide semiconductor heterostructure field effect transistor," IEEE Electron Device Letters, vol. 21, pp. 63-65, 2000.
[4] X. Hu, A. Koudymov, G. Simin, J. Yang, M. A. Khan, A. Tarakji, M. S. Shur, and R. Gaska, "Si3N4/AlGaN/GaN metal insulator semiconductor heterostructure field–effect transistors," Applied Physics Letters, vol. 79, p. 2832, 2001.
[5] P. D. Yet, B. Yang, K. K. Ng, J. Bude, G. D. Wilk, A. S. Halder, and J. C. M. Hwang, "GaN MOS-HEMT using atomic layer deposition Al2O3/ as gate dielectric and surface passivation," pp. 167-172, 2004.
[6] Y. Yue, Y. Hao, Q. Feng, J. Zhang, X. Ma, and J. Ni, "Study of GaN MOS-HEMT using ultrathin Al2O3 dielectric grown by atomic layer deposition," Science in China Series E: Technological Sciences, vol. 52, pp. 2762-2766, 2008.
[7] L. Zhi Hong, N. Geok Ing, S. Arulkumaran, M. Ye, T. Khoon Leng, F. Siew Chuen, V. Sahmuganathan, X. Tao, and L. Chee How, "High Microwave-Noise Performance of AlGaN/GaN MISHEMTs on Silicon With Al2O3 Gate Insulator Grown by ALD," IEEE Electron Device Letters, vol. 31, pp. 96-98, 2010.
[8] S. Yagi, M. Shimizu, M. Inada, H. Okumura, H. Ohashi, Y. Yano, and N. Akutsu, "Off-state drain current and breakdown voltage of AlGaN/GaN MIS-HEMT with multilayered gate insulator," physica status solidi (c), vol. 4, pp. 2682-2685, 2007.
[9] S. Yagi, M. Shimizu, H. Okumura, H. Ohashi, K. Arai, Y. Yano, and N. Akutsu, "1.8 kV AlGaN/GaN HEMTs with High-k/Oxide/SiN MIS Structure," pp. 261-264, 2007.
[10] B. Lu, O. I. Saadat, and T. Palacios, "High-Performance Integrated Dual-Gate AlGaN/GaN Enhancement-Mode Transistor," IEEE Electron Device Letters, vol. 31, pp. 990-992, 2010.
[11] B. Zhiwei, H. Yue, L. Hongxia, L. Linjie, and F. Qian, "Characteristics analysis of gate dielectrics in AlGaN/GaN MIS-HEMT," pp. 419-422, 2009.
[12] D. Zhuang and J. H. Edgar, "Wet etching of GaN, AlN, and SiC: a review," Materials Science and Engineering: R: Reports, vol. 48, pp. 1-46, 2005.
[13] T. Wu, Z.-B. Hao, G. Tang, and Y. Luo, "Dry Etching Characteristics of AlGaN/GaN Heterostructures Using Inductively Coupled H2/Cl2, Ar/Cl2 and BCl¬3/Cl2 Plasmas," Japanese Journal of Applied Physics, vol. 42, pp. L257-L259, 2003.
[14] L. Ji-Myon, C. Ki-Myung, P. Seong-Ju, and J. Hong-Kyu, "Inductively Coupled Cl2/Ar/O2 Plasma Etching of GaN, InGaN, and AlGaN," Journal of the Korean Physical Society, vol. 37, p. 842, 2000.
[15] Y. Han, S. Xue, W. Guo, Y. Luo, Z. Hao, and C. Sun, "Highly Selective Dry Etching of GaN over AlGaN Using Inductively Coupled Cl2/N2/O2 Plasmas," Japanese Journal of Applied Physics, vol. 42, pp. L1139-L1141, 2003.
[16] M. A. Khan, Q. Chen, C. J. Sun, J. W. Yang, M. Blasingame, M. S. Shur, and H. Park, "Enhancement and depletion mode GaN/AlGaN heterostructure field effect transistors," Applied Physics Letters, vol. 68, p. 514, 1996.
[17] W. B. Lanford, T. Tanaka, Y. Otoki, and I. Adesida, "Recessed-gate enhancement-mode GaN HEMT with high threshold voltage," Electronics Letters, vol. 41, p. 449, 2005.
[18] K. Ota, K. Endo, Y. Okamoto, Y. Ando, H. Miyamoto, and H. Shimawaki, "A normally-off GaN FET with high threshold voltage uniformity using a novel piezo neutralization technique," pp. 1-4, 2009.
[19] Dong-Seok Kim, "High performance in Normally-off Al2O3/GaN MOSFET Based on an AlGaN/GaN Heterostructure with a p-GaN buffer layer," Journal of the Korean Physical Society, vol. 58, p. 1500 ~ 1504, 2011.
[20] L. Yuan, H. Chen, and K. J. Chen, "Normally Off AlGaN/GaN Metal&2DEG Tunnel-Junction Field-Effect Transistors," IEEE Electron Device Letters, vol. 32, pp. 303-305, 2011.
[21] Y. Cai, Y. Zhou, K. M. Lau, and K. J. Chen, "Control of Threshold Voltage of AlGaN/GaN HEMTs by Fluoride-Based Plasma Treatment: From Depletion Mode to Enhancement Mode," IEEE Transactions on Electron Devices, vol. 53, pp. 2207-2215, 2006.
[22] N. Tsuyukuchi, K. Nagamatsu, Y. Hirose, M. Iwaya, S. Kamiyama, H. Amano, and I. Akasaki, "Low-Leakage-Current Enhancement-Mode AlGaN/GaN Heterostructure Field-Effect Transistor Using p-Type Gate Contact," Japanese Journal of Applied Physics, vol. 45, pp. L319-L321, 2006.
[23] Y. Uemoto, M. Hikita, H. Ueno, H. Matsuo, H. Ishida, M. Yanagihara, T. Ueda, T. Tanaka, and D. Ueda, "Gate Injection Transistor (GIT)& A Normally-Off AlGaN/GaN Power Transistor Using Conductivity Modulation," IEEE Transactions on Electron Devices, vol. 54, pp. 3393-3399, 2007.
[24] M. Kanamura, T. Ohki, T. Kikkawa, K. Imanishi, T. Imada, A. Yamada, and N. Hara, "Enhancement-Mode GaN MIS-HEMTs With n-GaN/i-AlN/n-GaN Triple Cap Layer and High-k Gate Dielectrics," IEEE Electron Device Letters, vol. 31, pp. 189-191, 2010.
[25] C. T. Chang, T. H. Hsu, E. Y. Chang, Y. C. Chen, H. D. Trinh, and K. J. Chen, "Normally-off operation AlGaN/GaN MOS-HEMT with high threshold voltage," Electronics Letters, vol. 46, p. 1280, 2010.
[26] R. Aggarwal, A. Agrawal, M. Gupta, and R. S. Gupta, "Analytical performance evaluation of AlGaN/GaN metal insulator semiconductor heterostructure field effect transistor and its comparison with conventional HFETs for high power microwave applications," Microwave and Optical Technology Letters, vol. 50, pp. 331-338, 2008.
[27] M. Esposto, S. Krishnamoorthy, D. N. Nath, S. Bajaj, T.-H. Hung, and S. Rajan, "Electrical properties of atomic layer deposited aluminum oxide on gallium nitride," Applied Physics Letters, vol. 99, p. 133503, 2011.
[28] N. Nepal, N. Y. Garces, D. J. Meyer, J. K. Hite, M. A. Mastro, and J. C. R. Eddy, "Assessment of GaN Surface Pretreatment for Atomic Layer Deposited High-kDielectrics," Applied Physics Express, vol. 4, p. 055802, 2011.
[29] Y. C. Chang, W. H. Chang, H. C. Chiu, L. T. Tung, C. H. Lee, K. H. Shiu, M. Hong, J. Kwo, J. M. Hong, and C. C. Tsai, "Inversion-channel GaN metal-oxide-semiconductor field-effect transistor with atomic-layer-deposited Al2O3 as gate dielectric," Applied Physics Letters, vol. 93, p. 053504, 2008.
[30] Y. Hori, C. Mizue, and T. Hashizume, "Process Conditions for Improvement of Electrical Properties of Al2O3/n-GaN Structures Prepared by Atomic Layer Deposition," Japanese Journal of Applied Physics, vol. 49, p. 080201, 2010.
[31] D. Gregušová, R. Stoklas, C. Mizue, Y. Hori, J. Novák, T. Hashizume, and P. Kordoš, "Trap states in AlGaN/GaN metal oxide semiconductor structures with Al2O3 prepared by atomic layer deposition," Journal of Applied Physics, vol. 107, p. 106104, 2010.
[32] S. Arulkumaran, T. Egawa, and H. Ishikawa, "Studies on the Influences ofi-GaN,n-GaN,p-GaN and InGaN Cap Layers in AlGaN/GaN High-Electron-Mobility Transistors," Japanese Journal of Applied Physics, vol. 44, pp. 2953-2960, 2005.
[33] H. Yang, Y. Son, S. Choi, and H. Hwang, "Improved Conductance Method for Determining Interface Trap Density of Metal Oxide Semiconductor Device with High Series Resistance," Japanese Journal of Applied Physics, vol. 44, pp. L1460-L1462, 2005.