現今半導體製程技術不斷地求新，因此IC相關產品開發過程也越來越困難。目前，最新的製程技術已經結合數位和類比變成混合型的電路設計。為了面對日新月異的複雜電路設計，我們必須要使用計算機輔助設計工具(CAD Tools)來減少整個IC設計過程的時間。如今，自動化佈局工具在數位電路設計方面已經被發展的很成熟；但是在類比電路設計方面，自動化佈局工具目前仍不太成熟。因為，類比電路佈局必須考慮很多特殊的限制，像對稱(symmetry)的需求、元件的匹配(matching)、電流密度，寄生效應(parasitic effect)等等。再加上很難在實際完成類比電路佈局之前，先正確的估算出寄生效應的影響，以避免類比電路性能的下降。所以，在本質上類比電路佈局設計是比數位電路有很大的困難度。本論文提出一個自動化佈局運算放大器的流程，並支援三種常用架構的運算放大器：摺疊疊接 (folded cascade)、電流鏡(current mirror)、伸縮(telescopic)。整套流程已經以C++實現並連結Laker輔助設計，並可通過DRC與LVS的驗證。

IC product development procedure is more and more difficult with the rapid advance in manufacturing process. Current technologies can even allow analog and digital circuits in the same chip, which are called mixed-signal circuits. In order to deal with the circuit design complexity, computer-aided design tools are required to shorten the IC design process. Nowadays, these automated layout tools are fairly well developed and commercially available to digital designs. But the automated layout tools for analog circuits are still in their infancy. Analog circuit layout must consider many special constraints, such as symmetrical requirements, device matching, current density, parasitic effect, etc.. However, it is difficult to accurately estimate the parasitic effects and fix them before the layout is completed. Therefore, the layout design is more difficult in analog designs than in digital designs. In this thesis, an automation flow of OP Amplifier layout is proposed. Three common OP Amplifiers, folded cascade、current mirror and telescopic, are supported in this flow. It has been implemented using C++ program and Laker. All the generated layout can pass DRC and LVS verification.

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