動態隨機存取記憶體（DRAM）在電子系統中扮演著重要的角色。近來，多通道動態隨機存取記憶體已被應用於三維或2.5維晶片中。由於多通道動態隨機存取記憶體在三維或2.5維晶片中測試操作困難，內建自我測試電路（built-in self-test）被視為一個好的測試方法。不同的內建自我測試電路已經被廣泛應用於動態隨機存取記憶體的測試。在先前已經有許多內建自我測試電路的技術被提出，而其大部分設計成可程式化（programmability）來支援不同的測試演算法。
在本論文中，我們首先針對各種應用於隨機存取記憶體的可程式化內建自我測試電路做探討。並且對於不同的可程式化內建自我測試電路進行詳盡的分析。隨後，我們提出了一個應用於動態隨機存取記憶體的混合式內建自我測試方法。所提出的混合式自我測試電路包含了一個支援對於金屬光罩改變（metal-change） 可程式化的微指令形式控制器（microcode-based controller） 和支援對於使用中模式暫存器和型態參數可程式化的有限狀態機形式控制器（FSM-based controller）。因此，如果所需的測試演算法沒有被預先存在唯讀記憶體中 （read-only-memory），我們僅需要改變金屬光罩來改變支援的測試演算法。現場可程式化可以滿足堆疊後測試（post-bond test）的需求，例如：驅動能力、 熱補償、不同個數的堆疊晶粒等。而我們也實際做出了應用於一個多通道動態隨機存取記憶體的混合式內建自我測試電路。實驗結果顯示，當應用在一個20Gb 4-通道動態隨機存取記憶體中單通道且支援行軍式（March）和非行軍式演算法與使用TSMC 90nm的製程時，我們的混合式自我測試電路僅需要18.2K邏輯閘數。最後，我們提出了一個應用於動態隨機存取記憶體的記憶體內建自我測試電路編譯器（compiler）。提出的內建自我測試電路編譯器可以產生出不同形式的內建自我測試電路，包括有限狀態機形式、微指令形式、可程式化微指令形式和我們所提出的混合式內建自我測試電路。

Dynamic random access memory (DRAM) is one key component in electronic systems. Recently,
multi-channel DRAMs have been proposed for three dimensional (3D) or 2.5D chips. Due to the
poor test accessibility, built-in self-test (BIST) method is considered a good approach for the postbond
testing of multi-channel DRAMs in 2.5D/3D chips. Various BIST schemes were presented to
test DRAMs. To support different test algorithms, most of those BISTs are designed as they have
the programmability of test algorithms.
In this thesis, we first survey existing programmable BIST schemes for RAMs. Comparison
of different programmable BISTs is conducted . Then, a hybrid BIST scheme for DRAMs is proposed.
The hybrid BIST consists of a microcode-based controller for supporting the metal-change
programmability of test algorithms and an FSM-based controller for supporting the in-field programmability
of mode registers and configuration parameters. Thus, if the needed test algorithms
are out of the test algorithms stored in the read-only-memory, only metal changing is needed to
change the supported test algorithms. The in-field programmability can meet the requirement of
post-bond test on the uncertainties of test thermal, number of stacked dies, driving strength of
drivers, and so on. We also have implemented the hybrid BIST for a multi-channel DRAM. Simulation
results show that only about 18.2K gates are needed to support March and non-March test
algorithms for a single channel within a 20Gb 4-channel DRAM using TSMC 90nm standard cell
library. Finally, a memory BIST compiler for DRAMs is proposed. The memory BIST compiler
can generate different types of memory BISTs including the FSM-based, microcode-based,
microcode programmable, and proposed hybrid BISTs.

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