可見光通訊技術 (Visible Light Communication, VLC)是目前正在發展中的一種利用可見光調變的通訊技術。具有高安全性與高速資料傳輸的特性，能夠應用在對高頻電磁波敏感之環境中，例如醫院病房中生理觀測儀器的資料傳輸，並防止干擾微弱生理訊號的測量。儘管未來將扮演照明主流的LED具有高頻寬以及快速脈衝響應的特性，然而由於傳輸環境與元件本身的雜訊干擾，以及依據傳輸距離遞增的通道衰減。將使得實際資料在傳輸時遭遇非理想的通道效應而與理想情況有一定誤差。因此在解決VLC系統中之通道衰減以及抵抗雜訊干擾以提升傳輸效率，將會是本論文之研究重點。
本論文針對VLC系統特性設計一套利用OFDM調變之規格，並以此規格設計VLC系統之OFDM基頻接收機。此接收機包含了時域頻域轉換、同步與等化的功能。同步功能包含有OFDM符碼邊界偏移估測和取樣時脈偏移估測與補償。等化部分包含通道效應估測與頻域等化器的資料回復。在本論文中將針對上述問題提出解決方法，使用Matlab與C語言建立系統模擬平台。電路部分以Verilog HDL描述，並使用TSMC-90nm製程來實現所設計之電路，以驗證電路設計的功能正確性。

Visible light communication (VLC) system is a technique which is being developed in modern. It utilizes the visible light to moderate for communication. The advantages of VLC are not only high speed transmission capability and the high security, but also can avoid high-frequency electromagnetic interference when transmitting data. For examples, the transmission of medical equipment in the hospital, it can prevent the interference of the bio-signal measurement. Although the LED with wide bandwidth and high-speed pulse response is the mainstream in the future, the noise of the transmission environment, the devices and the channel attenuation which is according to the transmission distance will cause the error during transmission. Therefore, how to solve the problems of channel attenuation and noise interference for transmission efficiency in VLC system is an important and crucial issue in my research.
We proposed the specification which utilizes the orthogonal frequency division multiplexing (OFDM) to modulate and use this to design the OFDM receiver in baseband of VLC system. This receiver including functions of time-domain transfers to frequency-domain, synchronous, and equalization. The synchronous function comprises symbol boundary detection, the estimation of sampling clock offset and compensate. The equalization includes channel effect detection and data recovering of frequency-domain equalizer. Thus, we proposed a new method to solve the problems that we mentioned. We established the simulation environment of the system by Matlab and C software, utilized Verilog HDL to finish the circuit, and realized the proposed in TSMC-90nm to verify the performance.

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