一應用於MPEG-4 AVC/H.264有效率且低成本之適應性可變長度編碼器設計之實現

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研究生：	張紓萍 Shu-Ping Chang
論文名稱：	一應用於MPEG-4 AVC/H.264有效率且低成本之適應性可變長度編碼器設計之實現 Implementation of an Efficient and Low Cost CAVLC for MPEG-4 AVC/H.264 Video Coding Application
指導教授：	蔡宗漢 Tsung-Han Tsai
口試委員:
學位類別：	碩士 Master
系所名稱：	資訊電機學院 - 電機工程學系 Department of Electrical Engineering
畢業學年度：	96
語文別：	英文
論文頁數：	97
中文關鍵詞：	適應性可變長度編碼器、有效率、低成本
外文關鍵詞：	h.264, CAVLC
相關次數：	點閱：20 下載：0
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為了達到更好的壓縮率,包含一適應性可變長度熵編碼(CAVLC)器的無失真熵編碼器（Entropy encoder）被MPEG-4 AVC/H.264影像編碼器採用.相較於傳統的可變長度編碼器,適應性可變長度熵編碼器可以達到更好的編碼效率;但是相對的演算法的複雜度也比較高.另一方面,由於適應性可變長度熵編碼器存在著高度的資料相關性,因此在硬體實現方面也會變的比較複雜.同時,產出率也是一個重要的考量,特別是應用於處理高解析度的視訊影像.
隨著處理的視訊有越高的解析度,在編(解)碼時使用一個有效率的適應性可變長度熵編(解)碼器是很重要的.這份論文提出一個有效率而且低成本的適應性可變長度熵編碼器,可應用在MPEG-4 AVC/H.264相關的視訊編碼器.被提出的架構中,包含兩個主要的概念以及三個技術.第一個概念是,整合架構中掃瞄和編碼的部分;另外一個概念是利用一副輸入暫存器來達到每一個4x4方塊之間的管線功能.另外三個技術分別為,簡化七個使用於編碼非零值的表格,利用六種模式來決定目前的4x4方塊的參數nC以及減少用於nC產生器的記憶體使用量.這三個技術可以提高我們的編碼效率並且降低我們的成本.
並且,本文提出的適應性可變長度熵編碼器架構,已被燒錄到FPGA(型號為Xilinx Virtex-4 XC4VLX60),並且聯合H.264/AVC原始編碼C語言程式做驗證工作.編碼所產生的檔案(bitstream.264),經過H.264/AVC原始解碼C語言程式的解碼之後,所得到的檔案(bitstream.yuv)可以被成功的播放.

In order to achieve the higher compression ratio, Context-Based Adaptive Variable Length Coding (CAVLC) is adopted as one of entropy encoder in MPEG-4 AVC/H.264 [1], [2]. Compared with the traditional entropy encoder, CAVLC can achieve better coding efficiency, but the algorithm complexity is higher. On the other hand, because of the data dependency in CAVLC, it results a complex CAVLC encoding in hardware implementation. At the same time, throughput is the other concern in CAVLC, especially for higher resolution video such as HDTV.
Deal with higher resolution of video information, encoding (or decoding) with an efficient CAVLC encoder is important. In this paper, an efficient and low cost CAVLC encoder is proposed for video coding applications of MPEG-4 AVC/H.264. Two main concepts are proposed to increase the throughput. One is the combination of scan phase and coding phase; the other is the block-based pipelining by the associated input buffer. We also propose three schemes to speed up the coding efficiency as well as reduce the area cost. One is to simplify the seven LEV-VLCN tables used by level coding. Another is to generate the nC value according to six block modes. The last one is to reduce the memory size used by nC generator.
And the proposed CAVLC design is downloaded to FPGA (Xilinx Virtex-4 XC4VLX60), and co-simulation with the h.264 source JM10.1 encoder c program for further verification. The encoded bitstream file (bitstream.264) can be decoded by h.264 source JM10.1 decoder c program and played successfully.

摘要 i
ABSTRACT ii
致謝 iii
CONTENT iv
LIST OF FIGURES vii
LIST OF TABLES ix
CHAPTER 1  INTRODUCTION 1
1	BACKGROUND 1
2	MOTIVATION 2
3	INTRODUCTION TO MPEG-4 AVC/H.264 3
3.1	INTER PREDICTION 9
3.1.1	TREE STRUCTURED MOTION COMPENSATION 9
3.1.2	MOTION VECTORS 10
3.1.3	MOTION VECTORS PREDICTION 10
3.2	INTER PREDICTION 11
3.3	DEBLOCKING FILTER 11
3.4	TRANSFORM AND QUANTIZATION 12
3.5	REORDERED 12
3.6	ENTROPY CODING 13
4	THESIS ORGANIZATION 14
CHAPTER 2  INTRODUCTION TO CONTEXT-BASED ADAPTIVE VARIABLE LENGTH CODING (CAVLC) 15
1	TYPICAL CAVLC ALGORITHM 16
1.1	ENCODE THE COEFF_TOKEN 17
1.2	ENCODE THE SIGN OF EACH TRAILINGONE 19
1.3	ENCODE THE LEVELS 19
1.3.1	ENCODING PROCEDURE 1 19
1.3.2	ENCODING PROCEDURE 2 20
1.4	ENCODE THE TOTAL_ZEROS 22
1.5	ENCODE THE RUN_BEFORE 23
2	AN EXAMPLE FOR CAVLC 23
CHAPTER 3  PREVIOUS WORKS ON CAVLC DESIGN 26
1	ARRANGEMENT OF PREVIOUS WORK 26
2	CONSIDERATION FOR PROPOSED DESIGN 30
2.1	BLOCK-BASED-PIPELINED 30
2.2	FORWARD READ RESIDUAL FROM EXTERNAL MEMORY 30
2.3	THE NC MODE DECISION 31
2.4	LEVEL ENCODER 32
CHAPTER 4  PROPOSED CAVLC ALGORITHM 33
CHAPTER 5  PROPOSED CAVLC ARCHITECTURE 35
1	ASSOCIATED INPUT BUFFER 37
2	INFORMATION STATISTICS 38
3	REGISTER (FOR DATA-BASED PIPELINING) 39
4	NC GENERATOR 39
4.1	POSITION GENERATION 40
4.2	UP BLOCK TOTALCOEFF MEMORY 41
4.3	CURRENT MB TOTALCOEFF REGISTER 43
4.4	NC MODE DECISION 44
5	CODING STAGE 48
5.1	LEVEL ENCODER 49
5.1.1	VLC NUMBER GENERATION 50
5.1.2	ADDRESS GENERATOR 51
5.1.3	MERGED TABLE FOR TABLE 52
5.1.4	ESCAPE CODE GENERATOR 54
6	BITSTREAM PACKER 54
7	CONTROL UNIT 57
8	ZERO SKIPPING MODE 57
CHAPTER 6  IMPLEMENTATION ON PLATFORM XILNX VIRTEX-4 XC4VLC60 59
1	INTRODUCTION TO XILINX VIRTEX-4 XC4VLC60 60
1.1	DEFAULT MODE 60
1.2	APPLICATION MODE (APP MODE) 61
2	SOFTWARE/HARDWARE CO-SIMULATION 62
2.1	THE ENCODING PROCEDURE OF DIFFERENT MB MODES 64
2.1.1	LUMA_INTRA16X16 MODE 65
2.1.2	LUMA 4X4 MODE 66
2.1.3	CHROMADC MODE 66
2.1.4	CHROMAAC MODE 67
2.2	WRITEDATA TO FIFO BY USER APPLICATION PROGRAM 68
2.3	READDATA FROM FIFO BY USER APPLICATION PROGRAM 70
2.4	READDATA FROM FIFO BY USER FPGA 71
CHAPTER 7  PERFORMANCE EVALUATION AND COMPARISON 73
1	SIMULATION RESULTS 73
1.1	EXPERIMENTAL ENVIRONMENT 74
1.2	EXPERIMENTAL RESULTS 74
2	IMPLEMENTATION RESULTS 76
3      SYNTHESIS RESULTS FOR FPGA 77
CHAPTER 8  CONCLUSION AND FUTURE WORK 79
1	CONCLUSION 79
2	FUTURE WORK 80
REFERENCES 82

                                

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