在本篇論文中，我們根據3GPP LTE-A的系統通道編碼傳輸規格，設計Radix-4架構高並行渦輪解碼器。在解碼時序上採用預處理滑窗解碼流程，來降低所需儲存的資料量並且增快約一倍的解碼速度。在解碼效能上，我們使用邊界資訊交換(NII)機制來改善因並行架構所造成的解碼性能損失。我們提出更簡單明瞭的解碼器與記憶體之間的資料交換網路，其中降低簡化交換網路所需要的控制訊號。除此之外，在解碼器的主要構成元件加法挑選補償器中，我們比較了各種實現的架構，並設計出在解碼效能與硬體面積兩者取捨中最為合理的組合。在硬體實現上，對硬體元件的量化與解碼性能的取捨做最佳化，達到最小面積的硬體與最接近演算法的解碼效能，我們設計實作出的解碼器跟演算法相比只有0.1dB的解碼效能損失，最後解碼器的硬體合成結果顯示操作頻率也能跟上3GPP LTE-A的傳輸規格限制。

In this thesis, we design the Turbo decoder applies to channel coding system for the 3rd Generation Partnership Project (3GPP) specification. The decoder implements the MLMAP algorithm with high radix and high parallel architecture. In timing chart of decoding, we utilize the sliding-window and warm-up scheme to improve the decoding period and performance. We utilize the NII scheme to compensate the performance loss caused by the high parallel architecture design. We propose the simpler and faster switch network than previous literatures. The memory area is reduced by reducing the number of memory blocks. The CSO unit is an important component of MLMAP implementation and we choose one structure as our best tradeoff from few different CSO structures. The proposed Turbo decoder can achieve operation frequency 425 MHz and throughput 950Mb/s per MLMAP decoder.

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