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| 研究生： |
黃俊誌 Jyun-jhih Huang |
|---|---|
| 論文名稱： |
三維圓柱形場效電晶體之模擬與分析 Simulation and Analysis in Three-Dimension Cylindrical MOSFETs |
| 指導教授： |
蔡曜聰
Yao-tsung Tsai |
| 口試委員: | |
| 學位類別： |
碩士 Master |
| 系所名稱： |
資訊電機學院 - 電機工程學系 Department of Electrical Engineering |
| 論文出版年： | 2015 |
| 畢業學年度： | 103 |
| 語文別： | 中文 |
| 論文頁數： | 52 |
| 中文關鍵詞： | 場效電晶體 、三維 、圓柱座標 、元件模擬 |
| 外文關鍵詞： | MOSFET, device simulation, cylindrical coordinates, three-dimensional |
| 相關次數： | 點閱：8 下載：0 |
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在本篇論文中，為了使我們的模擬程式能夠更精確於實際製程，我們將使用C語言來架構三維圓柱座標模擬程式，以提升模擬圓弧接面的準確度，並且比較傳統直角座標系統與我們所架構之圓柱座標系統的差異性。藉由模擬簡單的圓柱形電阻來驗證我們所架構的程式，並且探討改變元件的R半徑將會對元件的空乏區寬度、電場、臨限電壓造成什麼影響。最後我們更進一步的開發出新的contact方式：floating contact，以改善模擬環繞式結構的元件時，其body無法被contact的問題。
In this thesis, in order to make our simulation program more accurate at the actual manufacturing process, we will use the C language to build the three dimensional cylindrical coordinate simulation program. It can help us improve the accuracy of arc junction and compare Cartesian coordinate system with Cylindrical coordinate system. We can validate our program by simulating a cylindrical resistor, and discuss the effect on depletion width, electric field and threshold voltage caused by the variation of R radius. Finally, we have further developed a special floating contact to solve the problem that the body cannot be contacted directly in a device with surrounding gates .
[1] D. A. Neamen, Semiconductor physics and devices, 3rd ed., McGraw-Hill Companies Inc., New York, 2003.
[2] Yung-chin Lin, “Breakdown simulation of a spherical PN junction in cylindrical coordinates”, M. S. Thesis, Institute of EE, Nation Central University, Taiwan, Republic of China, 2012.
[3] Meng-syun Li, “Rectangular Transform of Trapezoidal Mesh and Its Application to Cylindrical MOSFETs”, M. S. Thesis, Institute of EE, Nation Central University, Taiwan, Republic of China, 2011.
[4] Hong-Chih Fang, “3D PN Diode Equation and Device Simulation with spherical Junction”, M. S. Thesis, Institute of EE, Nation Central University, Taiwan, Republic of China, 2012.
[5] A. L. Theng, “Realization of Gate-All-Around (GAA) SOI MOSFET Using Replacement Gate Mask, Electron Devices and Solid-State Circuits”, pp. 1129 – 1131, 2007.
[6] Jae Young Song, “Design Optimization of Gate-All-Around (GAA) MOSFETs, IEEE Transactions on Nanotechology”, Vol. 5, pp. 186 - 191, 2006.
[7] Z. X. Chen, “Realization of Ni Fully Silicided Gate on Vertical Silicon Nanowire MOSFETs for Adjusting Threshold Voltage”, IEEE Electron Device Letters, Vol. 32, pp. 1495 - 1497, 2011.
[8] Xiang Li, “Vertically Stacked and Independently Controlled Twin-Gate MOSFETs on a Single Si Nanowire, IEEE Electron Device Letters”, Vol. 32, pp. 1492 – 1494, 2011.
