繞線(routing)是實體設計(physical design)的最後一個步驟，關係著整個晶片的成功與否，因此是超大型積體電路(VLSI)設計領域中很重要的一環。繞線是針對一個已通過電路分群(circuit partitioning)、佈局規劃(floorplanning)與擺置(placement)等步驟的電路，進行所有連線(net)上信號節點(pin)的連接動作。
繞線完成度(routability)一直以來都是繞線問題中的重要議題。除此之外，隨著製程的進步，愈來愈多且複雜的製造限制需要在繞線時被考量，如障礙物(obstacle)、偏好方向(preferred direction)及變換方向區域(switch region)。因此，如何產生一個高繞線完成度的繞線結果且符合製造上的限制是實體設計的一大挑戰。
本研究提出了一個以連接圖形(connection graph)為基礎、強健且有效的繞線演算法。此演算法可處理偏好方向、變換方向區域與不同層擁有不同網格大小等製造限制。實驗結果顯示，本研究提出的演算法可以針對每一連線建立高品質(high-quality)的繞線樹(routing tree)，並且得到一個高繞線完成度(high-routability)的繞線結果。

Routing is very important for VLSI designs since it is the last stage of the physical design and is related to the success of a chip. Routing is aimed to connect all pins of each net for a circuit, which has passed circuit partitioning, floorplanning, and placement.
Routability is always an important issue for routing. Besides, as technology advances, more and more complicated manufacturing constraints are needed to be considered in routing, such as obstacles, preferred directions, and switch regions. Therefore, it is a tremendous challenge to generate high-routability routing results with meeting modern manufacturing constraints.
In this thesis, we propose a robust and effective routing algorithm based on a connection graph method. The algorithm can handle preferred directions, switch regions, and different pitch values for different layers. Experimental results show that our algorithm can construct a high-quality routing tree for each net, and obtain a high-routability routing result.

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