在本論文中我們設計並實現了應用於LTE/LTE-A的高吞吐量渦輪碼設計。為了支援高傳輸量，使用了8套 radix-4 MAP平行SISO解碼器。而在解碼流程上，我們採用了滑動視窗解碼來提升解碼速度，另外預熱處理機制則用來補償多平行架構產生的解碼效能損耗。
接著我們運用了四種技巧來改善硬體設計。首先利用原地處理的概念將MAP解碼器內的α記憶體大小縮減一半，使得硬體總面積下降；再來藉著將前半次及後半次疊代運算疊合以縮減中間的解碼時間，使得解碼效率得到提升，進一步也提升了渦輪解碼器的吞吐量；第三項著重在交換網路的部分，我們更進一步地利用了QPP交錯器的特性，設計出一套擁有單純旋轉器及控制邏輯的新式交換網路，減少了交換網路的運算次數；最後一項改善是解決了多平行配上高基數演算的高吞吐量設計下，額外產生的特殊記憶體衝突。利用簡單的判斷條件配合額外的多工器交換存取或寫入的位址及資料。
在實作的部分利用 Design Compiler及 IC Compiler合成並選用TSMC 90nm CMOS製程，最後驗證我們的渦輪碼設計可以操作在406MHz下，並提供511Mbps的高吞吐量。

In this paper, we design and implement a high-throughput turbo decoder for the 3rd Generation Partnership Project (3GPP) Long Term Evolution-Advanced (LTE-advanced) system. To support the high data rate, we adopts eight radix-4 parallel soft-in/soft-output MAP decoders. We adopt MAP decoding with sliding window mechanism to decrease decoding time. And we also use the warm-up scheme to compensate the performance loss. Besides, The properties of quadratic permutation polynomial (QPP) interleaver are exploited to reduce the complexity of the switch network between memory and MAP decoder.
Four techniques are used to improve the hardware design. First, the in-place algorithm is adopted to decrease the size of α-memory in MAP decoder , and hence the overall area can be reduced. Next, the processing periods of the last window in the first half iteration and the first window in the second half iterations are scheduled to be overlapped, Consequently, the decoding time is reduced and the throughput of the turbo decoder can be enhanced. The interconnection network is designed elaborately. A new interconnection network is proposed with a simple rotator and control logic. Using simple conditional judgement with extra multiplexers to exchange the address and memory data, we can support parallel processing of the turbo decoding. In addition, We achieve non-conflict memory access under high parallel and high radix hardware design for 188 modes .
From synthesis result, this work can operate at 406 MHz to offer decoding data rate up to 511 Mbps in 90nm CMOS technology.

[1] C. Berrou, A. Glavieux and P. Thitimajshima, "Near Shannon limit error-correcting coding and decoding: Turbo Codes," in Proc. IEEE Int. Conf. Commun. ICC’93, Geneva, Switzerland, May 1993, pp. 1064-1070.
[2] L. Bahl, J. Cocke, F. Jelinek, and J. Raviv. “Optimal decoding of linear codes for minimizing symbol error rate (Corresp.),” IEEE Trans. Inf. Theory, vol. 20, 1974, pp. 284-287,.
[3] J. Sun and O. Y. Takeshita. “Interleavers for Turbo codes using permutation polynomials over integer rings,” IEEE Trans. Inform. Theory, vol. 51, no. 1, Jan.2005, pp.101-119.
[4] P. Robertson, P. Hoeher and E. Villebrun, “Optimal and Sub-Optimal Maximum A Posteriori Algorithms Suitable for Turbo Decoding,” European Trans. Telecommun, vol. 8, no. 2, Mar.1997, pp. 119-125.
[5] A. J. viterbi. “An intuitive justification and a simplified implementation of the MAP decoder for convolutional codes.” IEEE J. Sel. Areas Commun, vol. 16, pp.260-264, 1998.
[6] A. Nimbalker, Y. Blankenship, B. Classon, and T. K. Blankenship. “APP and QPP Interleavers for LTE Turbo Coding.” in Proc. IEEE WCNC, 2008, pp. 1032-1037.
[7] J. Dielissen and J. Huisken, “State Vector Reduction for Initialization of Sliding Windows
MAP,” in Symp. Turbo Codes, Sep. 2000, pp. 387–390.
[8] C. Stuber, and et al. “A 390Mbps 3.57mm2 3GPP-LTE turbo decoder ASIC in 0.13 um CMOS,” in Proc.IEEE ISSCC, Feb. 2010, pp. 274–276.
[9] C.-H. Lin, E.-J. Chang, C.-Y. Chen, and A.-Y. Wu, “A 0.16nJ/bit/iteration 3.38mm2 turbo decoder chip for WiMAX/LTE standards,” in Proc. IEEE ISIC, pp. 178-181, Dec. 2011.

[10] T. Ilnseher, M. May, and N. Wehn, “A multi-mode 3GPP-LTE/HSDPAturbo decoder,” in Proc. IEEE ICCS, Nov. 2010, pp. 336–340.
[11] Eid M. Abdel-Hamid, Hossam A. H. Fahmy, Mohamed M. Khairy, Ahmed F. Shalash, “Memory conflict analysis for a multi-standard, reconfigurable turbo decoder,” ISCAS 2011: 2701-2704.
[12] Ahmed, Ashfaq; Awais, Muhammad; Rehman, Ata Ur; Maurizio, Martina; Masera, “A
High Throughput Turbo Decoder Vlsi Architecture for 3Gpp Lte Standard,” in Proc. IEEE
INMIC, Dec.2011, pp. 340–346.
[13] C.-C. Wong, Y.-Y. Lee, and H.-C. Chang, "A 188-size 2.1mm2 reconfigurable turbo
decoder chip with parallel architecture for 3GPP LTE system," in Proc. IEEE Symp. VLSI
Circuits, June 2009, pp. 288-289.
[14] Jen-Yu Hou, “Design and Implementation of Turbo Decoder for 3GPP-LTE Advanced
Systems,” Master thesis, National Centural University, July, 2011.