電子系統層級上之設計H.264編碼系統於單晶片網路系統平台

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研究生：	林家宏 Chia-Hung Lin
論文名稱：	電子系統層級上之設計H.264編碼系統於單晶片網路系統平台 An Electronic System Level Design of H.264 Encoding System on Network-on-Chip Platform
指導教授：	蔡宗漢 Taung-Han Tsai
口試委員:
學位類別：	碩士 Master
系所名稱：	資訊電機學院 - 電機工程學系 Department of Electrical Engineering
畢業學年度：	96
語文別：	英文
論文頁數：	101
中文關鍵詞：	單晶片網路、交易層級、電子系統層級
外文關鍵詞：	NoC, TLM, H.264, SystemC, ESL
相關次數：	點閱：11 下載：0
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隨著系統晶片日益複雜，複雜度不斷的增加，此時系統設計者必須找尋一種新的設計方法，而能夠去處理系統晶片的複雜度，且能縮短設計時程來提昇產品的生產率。一種明顯解決的方法則是提高設計的抽象層次。然而，對於系統設計者而言較關心的則是系統的架構、軟體/硬體的效能、以及通訊協定。因此，電子系統層級設計的方法能夠去滿足複雜的系統設計，且此方法能夠提高模擬的速度及幫助系統效能的估算。所以我們能夠反覆的分析系統架構及設計而不在是以一種架構來設計。
在這篇論文裡，我們以SystemC語言在交易層(Transaction-Level)的抽象層次來完成網路晶片(Network-on-Chip)平台。此網路晶片平台基本模組包含了:五個方向的交換器、傳輸鏈結、以及各式各樣的週邊模組。我們除了完成系統網路晶片平台外，我們亦完成一個H.264影像編碼器來當系統的平台應用，且以電子系統層級的設計方法去設計網路晶片平台的模組、設計空間的勘查方面的工作、及對系統效能做評估。我們依該方法在循序可執行程式碼和暫存器傳輸層級間建立抽象模型。讓我們可以在短時間之內評估系統的效能並且萃取重要的資訊以及能在設計過程中比較直覺的完成設計。
最後，整個網路晶片系統平台能夠模擬且驗證應用系統的功能正確性以及在傳輸鏈結上萃取動態的資訊，來分析解決系統的瓶頸所在。

With complexities of Systems-on-Chip rising almost daily, the system designers have been searching for new methodology that can handle the complexities with increased productivity and decreased times-to-market. The obvious solution that comes to mind is increasing the level of abstraction. However the system designers care about are system architectures, Hardware/Software (HW/SW) performance, and the communication protocols. Furthermore, the electronic system level (ESL) design methodology can satisfy the requests on complex design with relative high simulation speed well performance evaluation. We can use it in the iterative design process rather than just in the early system architecting phase.
In this thesis, we implement a transaction level model (TLM) Network-on-Chip platform with SystemC. The basic modules: variable wrapper, 5-ports switch, transmission link and heterogeneous peripherals. In addition to NoC platform, we also implement the H.264 encoder as the system application, and apply a design methodology at ESL to do design modeling, design space exploration and performance evaluation. We base on it to establish abstract model between the sequential executable codes and the register transfer level (RTL) description. We are able to evaluate performance in relatively short time, obtain important information and complete the design more instinctively.
Finally, the NoC platform will run the whole system simulation to verify the functional model and collect the dynamic information on the transmission link and IPs to analysis the bottle-neck of the system.

摘要----------------------------------------------------i
ABSTRACT------------------------------------------------ii
LIST OF FIGURE------------------------------------------vii
LIST OF TABLES------------------------------------------x
CHAPTER 1  INTRODUCTION---------------------------------1
1  	MOTIVATION-------------------------------------1
2	CONTRIBUTION-----------------------------------6
3	THESIS ORGANIZATION----------------------------6
CHAPTER 2  SYSTEMC LANGUAGE OVERVIEW--------------------8
1	SYSTEMC FEATURES-------------------------------9
2	MODULES AND PROCESSES--------------------------10
3	INTERFACES, PORTS AND CHANNELS-----------------12
3.1	INTERFACES-------------------------------------13
3.2	PORTS------------------------------------------13
3.3	CHANNELS---------------------------------------14
4	SYNCHRONIZATION--------------------------------15
5	TIMING-----------------------------------------16
6	HARDWARE-ORIENTED DATA TYPE--------------------16
CHAPTER 3  TRANSACTION LEVEL MODELING-------------------17
1	ACCURACY MODEL OF TLM--------------------------17
2	TLM FOR ARCHITECTURE EXPLORATION---------------19
CHAPTER 4  INTRODUCTION OF THE NOC----------------------24
1	ARCHITECTURES OF THE NOC-----------------------24
2	COMMUNICATION PROTOCOLS------------------------27
3	COMPONENTS OF THE NOC--------------------------30
3.1	SWITCH-----------------------------------------30
3.2	Network Interface------------------------------31
CHAPTER 5  H.264 ENCODER SYSTEM-------------------------33
1	INTRODUCTION-----------------------------------33
2	INTRA PREDICTION-------------------------------35
3	TRANSFORM AND QUANTIZATION---------------------37
4	CONTEXT-BASED ADAPTIVE VARIABLE LENGTH CODING--40
5	INTER PREDICTION-------------------------------43
6	IN-LOOP DEBLOCKING FILTER----------------------45
CHAPTER 6  IMPLEMENTATION-------------------------------48
1	DESIGN ENVIRONMENT-----------------------------48
2	NETWORK-ON-CHIP PLATFORM-----------------------50
2.1	FLIT FORMAT DEFINITION IN SYSTEMC--------------51
2.2	DEVELOPING A SWITCH MODEL----------------------53
2.3	DEVELOPING A TRANSMISSION LINK MODELING--------55
3	ANALYSIS MODELING------------------------------60
3.1	CHANGE THE MASTER PORT INTERFACE---------------61
3.2	CHANGE THE SLAVE PORT INTERFACE----------------62
3.3	INITIALIZE THE MASTER DEVICES------------------63
3.4	INITIALIZE THE SLAVE DEVICES-------------------64
3.5	ANALYZE TRANSACTIONS---------------------------65
3.6	ANALYZE CONTENTION-----------------------------66
3.7	ANALYZE LATENCIES------------------------------67
4	H.264 ENCODER MODULE IN SYSTEMC----------------68
5	HDL PROXY MODULE-------------------------------73
CHAPTER 7  EXPERIMENT RESULTS---------------------------76
1	EXPERIMENT ENVIRONMENT-------------------------76
2	VERIFICATION AND ANALYSIS----------------------79
2.1	FUNCTIONAL VERIFICATION------------------------80
2.2	PLATFORM ANALYSIS------------------------------84
3	SYSTEMC/RTL CO-SIMULATION----------------------86
CHAPTER 8  CONCLUSION AND FUTURE WORK-------------------89
1	CONCLUSION-------------------------------------89
2	FUTURE WORK------------------------------------90
REFERENCES----------------------------------------------91
APPENDIX------------------------------------------------94

                                

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