As the technology progress, CPU performance doubles 18 months a period. Now the development of VLSI is faced with physics limitation. For past years, CPU performance is increased by raised up CPU frequencies. But by the effect of physics limitation, CPU frequencies can’t be grown unlimitedly. So the number of cores on a chip is increased from single core to multi-core. As the number of cores on a chip growing, we introduce computer network concept into the chip. Network-on-Chip (NoC) provides a packet switching based communication to connect components on the chip. In the meantime, the introduction of RF (radio frequency) interconnect brings the new opportunity for high data rate, low latency and low power consumption for millimeter range on-chip communication for next chip generation. In this paper, we study wireless Network-on-Chip (WNoC) with RF links. We first present the benefit of WNoC and disadvantage of WNoC. Then we design a group-based channel access scheme for WNoC to solve the problem of contention and hidden terminal while data transmitted and use an OMNeT++ based NoC simulator to simulate our design.

隨科技的進步，處理器效能每18個月為周期做兩倍的成長。然而，受到物理的限制，在過去靠著提升時脈來增加效能方法已經到了瓶頸。因此，處理器開始由單核心的架構轉為多核心發展。隨著核心數量的提升，傳統的匯流排架構成為多核心處理器裡，效能與設計的瓶頸。為了改進處理核心與核心之間資料交換的問題，我們把電腦網路的概念帶進到了處理器。此種新的架構使用了電腦網路中分封交換技術來傳遞晶片中各元件的資料。同時，無線射頻技術的進步，使得晶片內通訊透過無線的方式傳輸變的可能，為下一代的晶片提供了高速率、低延遲和低功耗的傳輸方式。在這篇論文中，我們研究了整合無線射頻技術的無線網路晶片，介紹其優點與問題，並對此設計了一個分群的機制和其路由的方法，來解決在無線傳輸的機制中，資料傳輸碰撞的問題。而在最後，我們使用OMNeT++為基礎的網路晶片模擬器來模擬我們的方法。

[1] Radu Marculescu, Umit Y. Ogras, Li-Shiuan Peh, Natalie Enright Jerger and Yatin Hoskote, "Outstanding Research Problems in NoC Design: System, Microarchitecture, and Circuit Perspectives," IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, Vol. 28, 3-21, January 2009.
[2] M.-C. F. Chang, V. Roychowdhury, L. Zhang, H. Shin, and Y. Qian, "RF/wireless interconnect for inter- and intra-chip communications," Proceedings of The IEEE, vol. 89, no. 4, pp. 456–466, April 2001.
[3] B. A. Floyd, C.-M. Hung, and K. K. O, "Intra-chip wireless interconnect for clock distribution implemented with integrated antennas, receivers, and transmitters," IEEE Journal of Solid-State Circuits, vol. 37, no. 5, pp. 543–552, May 2002.
[4] K. Kimoto and T. Kikkawa, “Transmission characteristics of gaussian monocycle pulses for inter-chip wireless interconnections using integrated antennas," Japanese Journal of Applied Physics, vol. 44, no. 4B, pp. 2761–2765, 2005.
[5] T. Kikkawa, P. K. Saha, N. Sasaki, and K. Kimoto, "Gaussian monocycle pulse transmitter using 0.18µm cmos technology with on-chip integrated antennas for inter-chip uwb communication," IEEE Journal of Solid-State Circuits, vol. 43, no. 5, pp. 1303–1312, May 2008.
[6] W. M. N. Sasaki, K. Kimoto and T. Kikkawa, "A single-chip ultra-wideband receiver with silicon integrated antennas for inter-chip wireless interconnection," IEEE Journal of Solid-State Circuits, vol. 44, no. 2, pp. 382–393, February 2009.
[7] Dan Zhao, Yi Wang, Jian Li and Takamaro Kikkawa, “Design of multi-channel wireless NoC to improve on-chip communication capacity,” Proceedings of the 2011 Fifth IEEE/ACM International Symposium on Networks on Chip (NoCS), pp. 177-184, July 2011.
[8] K. Kawasaki, Y. Akiyama, K. Komori, M. Uno, H. Takeuchi, T. Itagaki, Y. Hino, Y. Kawasaki, K. Ito, and A. Hajimiri, "A millimeter-wave intra-connect solution," in Digest of International Solid-State Circuits Conference, 2010, pp. 413–415.
[9] International Technology Roadmap for Semiconductors: Semiconductor Industry Association, 2006.
[10] S. B. Lee et al., "A scalable micro wireless interconnect structure for CMPs," in Proc. ACM Annu. Int. Con. Mobile Comput. Network. (Mo-biCom), 2009, pp. 20–25.
[11] D. DiTomaso et al., "iWise: Inter-router wireless scalable express chan-nels for Network-on-Chips (NoCs) architecture," in Proc. Annu. Symp. High Performance Interconnects, 2011, pp. 11–18.
[12] S. Deb, A. Ganguly, P. Pande, D. Heo, and B. Belzer, "Wireless NOC as interconnection backbone for multicore chips: Promises and chal-lenges," IEEE J. Emerg. Sel. Topics Circuits Syst., Jun. 2012.M.-C. Frank Chang, Eran Socher, Sai-Wang Tam, Jason Cong and Glenn Reinman, "RF Interconnects for Communications On-chip," Proceedings of ISPD ''08 Proceedings of the 2008 international symposium on Physical design, pp. 191-202, February 2008.
[13] D. Zhao and Y. Wang, “SD-MAC: Design and Synthesis of a Hardware-efficient Collision-free QoS-aware MAC Protocol for Wireless Network-on-chip,” IEEE Transaction on Computer, vol. 57, no. 9, pp. 1230–1245, September 2008.
[14] A. Varga et al. ,"The OMNeT++ discrete event simulation system", In Proc. of the European Simulation Multiconference (ESM’2001), pp. 319-324, 2001.
[15] Y. Ben-Itzhak, E. Zahavi, I. Cidon, and A. Kolodny, "NoCs simulation framework for OMNeT++", in Proc. of NOCS, pp.265-266, 2011.