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研究生： 呂昭信
Chao-Hsin Lu
論文名稱： 2.5Gbps光纖收發機設計
2.5Gbps Optical Transceiver
指導教授： 陳巍仁
Wei-Zen Chen
口試委員:
學位類別： 碩士
Master
系所名稱： 資訊電機學院 - 電機工程學系
Department of Electrical Engineering
畢業學年度： 89
語文別： 中文
論文頁數： 93
中文關鍵詞： 相位鎖相迴路 、光纖 、收發機 、接收器 、資料回覆器 、傳送器
外文關鍵詞： Phase-Locked Loop, Optical, Transceiver, Receiver, Data Recovery, Transmitter
相關次數： 點閱：11  下載：0 
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    • 光纖網路應用在高速和長程傳輸通訊已經變成一個主要的趨勢。傳統上，光纖收發機是使用昂貴的砷化鉀製程。今日，數GHz的射頻ICs已經成功的使用次微米的CMOS和BicMOS製程來達到。而以加快降低光纖元件的成本為目標，本篇論文探討使用矽製程來達成光纖收發機的電路設計技術。以及研究的目的是為了達到2.5Gbps的光纖收發機電路。
    在傳送器端，一個2伏、2.5Gbps的CMOS資料合成器被提出。高速的平行至串列的轉換是使用一個低抖動和八個相位的PLL來做以時間區分的多工器。其最大的轉換速率超過了312.5Mbytes/s。更進一步地，一個雷射驅動器被使用來驅動一個外加的雷射電晶體。其製作在0.8mm BiCMOS的製程，可達到30mA調變電流、10mA偏壓電流和操作在3Gbps下。經量測的結果，其眼圖符合OC-48的要求。
    接收器的前端ICs發展在這一次的工作之中，包含了一個轉阻放大器和一個限制放大器，它們是利用0.35mm CMOS製程來達到，且操作在3V的電壓下。轉阻放大器提供一個54dBW和2.5GHz的-3dB頻寬。而限制放大器則是有4mv的敏感度、2.2GHz的-3dB頻寬和40dB的增益。另外，再提出一個使用3倍取樣技術的資料回覆器電路。
    所有在這篇論文中所提出之電路皆有完整的探討和測量。其效能大大地顯視出未來光纖通訊在CMOS製程上SoC化的可行性。


    At the transmitter side, a 2V and 2.5Gbps CMOS data serializer has been proposed. High speed parallel to serial data conversion is achieved by means of time-division multiplexer toggled by a low jitter and 8-phases PLL. The maximum conversion rate is in excess of 312.5Mbyte/sec. Moreover, a laser diode driver in the succeeding stage has been implemented to drive an external laser diode. Fabricated in a 0.8mm BiCMOS process; the driver circuit delivers a modulation current of 30mA, a biased current of 10mA and is capable of operating at 3Gbps. The measured eye diagram meets the transition mask required by OC-48.
    The front-end ICs at the receiver side developed in this work include a transimpedance amplifier (TIA) and a limiting amplifier (LA), which are implemented in 0.35mm CMOS technology and operated under a 3V supply. The TIA provides a conversion gain of 54dBW with a —3dB bandwidth of 2.5GHz. The limiting amplifier achieves an input sensitivity of 4mv, -3dB bandwidth of 2.2GHz and conversion gain of 40dB. In addition, an oversampling by three data recovery circuits architecture has been proposed.
    All the circuit blocks described in this thesis have been thoroughly investigated and measured. The promising performances demonstrated strong potentials for future SoC solutions of optical transceivers in CMOS technology.

    Abstracti Contentiii List of Figuresvi List of Tablesix Chapter 1Introduction1 1.1Motivation1 1.2Thesis Organization2 Chapter 2Phase-Locked Loop5 2.1Introduction5 2.2PLL Architecture6 2.2.1PLL Linear Model7 2.2.2Z-domain Stability8 2.3Building Blocks of the PLL10 2.3.1Phase Frequency Detector10 2.3.2Charge Pump13 2.3.3Loop Filter14 2.3.4Voltage Controlled Oscillator14 2.3.5Divider17 2.4Noise Analysis19 2.5Measurement21 Chapter 3Transmitter24 3.1Introduction24 3.2Data Serializer25 3.3Encoder26 3.4Serializer26 3.5Simulation of Serializer28 3.6Laser Diode Driver30 3.6.1Laser Diode30 3.6.2Block of LD Driver33 3.7Measurement of LD36 Chapter 4Front-End Circuits Design39 4.1Introduction39 4.2Front-End Circuits40 4.3Active Inductor41 4.4Transimpedance Amplifier43 4.4.1Low Input Impedance TIA44 4.4.2Gm Enhancement Technique45 4.4.3TIA Implementation47 4.4.4Simulation Results of TIA48 4.5TIA Measurement Results50 4.6Limiting Amplifier52 4.6.1Gain Cells54 4.6.2Offset Cancellation54 4.6.3Gain Stage Optimization55 4.7Measurement of LA58 Chapter 5Data Recovery61 5.1Introduction61 5.2Data Recovery Architecture62 5.2.1PLL-Based Data Recovery62 5.2.2Oversampling-Based Data Recovery63 5.3Building Blocks of Data Recovery64 5.3.1RX-PLL64 5.3.2Oversampled Block65 5.3.3Phase Decision66 5.3.4Data Decision68 5.3.5Preamble Detector69 5.3.6Byte Alignment69 5.3.7First-In First-Out Memory (FIFO)72 5.4Data Recovery Simulation Results73 Chapter 6Conclusion74 Bibliography77

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