隨著製程演進，漏電流功率消耗也快速地逐漸增加，使用電源閘設計來降低漏
電流以及動態功率消耗，已經成為一個常被使用的技術。而在設計電源閘電路的時
候，會遇到兩個經常被討論到的關鍵問題：電源閘的尺寸以及喚醒時程的設計。然
而，要解決這兩個關鍵問題都會需要同一個資訊，就是喚醒電流波形。大部分已知
的研究，都是假設此電流波形可以在電晶體層級得到。雖然這些研究可以在電晶體
層級得到詳細、準確的電流波形，但是通常會需要非常大的模擬時間。直到現在，
也沒有非常多的研究在針對電源閘電路，建立快速有效率的電流波形模型，來分析
喚醒電流造成的效應。因此，我們提出了一個使用資料庫格式（standard cell
library）的電流模型，來估測喚醒電流的方法。此方法會依照電源閘電路在喚醒
時，各個元件的輸入端的數值，去尋找合適的切換電流波形，加上電壓降的波形修
正方法，最後再加上電源閘影響的電流波形，來建立喚醒電流模型。當模型建立好
以後，只需要給予電源閘的等效電阻、電容值，便可以在設計階段利用此模型估測
任意輸入向量的喚醒電流模型。而實驗結果也證明，我們的閘層級電流模型確實可
以產生足夠準確、相似度逼近電晶體層級的電流波形，提供使用者可以在設計初期
做初步的分析。

Duo to the fast growth of leakage power dissipation,
power-gating technique is a often used to reduce leakage
power and dynamic power simultaneously. While designing a
power gating design, two critical issues are often
discussed: sleep transistor sizing and wakeup scheduling.
However, solving the two critical issues requires the same
essential information, the supply current waveform of the
main circuits. Most existing approaches assume that the
current information of the main circuits can be obtained
from transistor-level simulation. Although this approach can
obtain highly accurate current waveforms, it often requires
heavy simulation overhead. Until now, not too many
researches focus on studying a fast and efficient current
model for power gating designs to analyze the wake-up
current impacts. Therefore, a gate-level current model is
proposed using standard cell library format to estimate the
wake-up current. According to the input values of each cell,
the proposed method will choose an existing switching
current waveform and modify it to build the wake-up current
model. Thus, the wake-up current waveform can be obtained by
the proposed approach without extra characterization, except
the input values and the equivalent resistance and
capacitance of the power gate. The experimental results show
that the proposed gate-level wake-up current model can
provide accurate enough current waveform to help designer
analyze the rush current effects at early design stages.

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