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研究生： 孫世洋
Shi-Yang Sun
論文名稱： 以符碼間干擾偵測技術實現自適應等化器之5 Gbps半速率時脈與資料回復電路
A 5 Gbps Half-Rate Clock and Data Recovery with Adaptive Equalizer Using ISI Detecting Technique
指導教授： 鄭國興
Kuo-Hsing Cheng
口試委員:
學位類別： 博士
Doctor
系所名稱： 資訊電機學院 - 電機工程學系
Department of Electrical Engineering
論文出版年： 2016
畢業學年度： 104
語文別： 中文
論文頁數： 194
中文關鍵詞： 資料與時脈回復電路 、鎖相迴路 、自適應等化器
外文關鍵詞： Clock and Data Recovery (CDR), Phase Locked Loop (PLL), Adaptive Equalizer (EQ)
相關次數： 點閱：15  下載：0 
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    • 隨半導體產業發展與電腦相關產業的興起，資料傳輸頻寬逐漸上升，傳統並列傳輸方式漸漸被串列傳輸取代，例如DisplayPort、SATA、USB、及PCI-E 等皆使用串列傳輸介面。本論文參考USB 3.1 Gen1規格實現一個具自適應等化器之資料與時脈回復電路。
    本論文將自適應等化器控制機制內嵌於資料與時脈回復電的相位偵測器中，使得原本兩個獨立的迴路能夠結合在一起，以達到降低硬體複雜度，與此同時，利用混合式半速率二進位相位偵測器與電流模式電容放大技術來達到低的功率消耗與降低面積。本論文使用TSMC 90 nm (TN90GUTM) 1P9M之製程來實現，電路操作電壓為1 V，輸入資料速率為5 Gbps時，回復時脈速率為2.5 GHz，峰對峰值抖動量15.56 ps，均方根值抖動量為2.27 ps，在通道長度為0-m時(短通道)，等化後資料的峰對峰值抖動量為21.33 ps，方均根值抖動量為3.41 ps，在通道長度為1.5-m時(長通道) ，等化後資料的峰對峰值抖動量為24 ps，方均根值抖動量為4.84 ps。功率消耗為21.9 mW，其中資料與時脈回復電路之功率消耗為15.1 mW，自適應等化器之功率消耗為6.8 mW，晶片面積為1.38 mm2，核心電路面積為0.13 mm2。

    In recent year, according to rapid development of process and computers, the data bandwidth increases progressively. The serial data transmission is widely used for bus instead of parallel data transmission, for example, DisplayPort, SATA, USB, and PCI-E. This study presents a clock and data recovery (CDR), and takes USB 3.1 Gen1 specification as reference material.
    In this thesis, the control loop of adaptive equalizer is embedded in phase detector of clock and data recovery to achieve low hardware complexity, meanwhile, using hybrid phase detector and current mode capacitance magnification method achieve small area and low power. This proposed was implemented by TSMC 90 nm (TN90GUTM) 1P9M process with 1V supply voltage. When CDR operates at 5 Gbps, the frequency of recovered clock is 2.5 GHz, peak-to-peak jitter of recovered clock is 15.56 ps, RMS jitter of recovered clock is 2.27 ps. When channel length is 0-m (short channel), peak-to-peak jitter of equalized data is 21.33 ps, RMS jitter of equalized data is 3.41 ps. When channel length is 1.5-m (long channel), peak-to-peak jitter of equalized data is 24 ps, RMS jitter of equalized data is 4.84 ps. The total power consumption of this work is 21.9 mW, the power consumption of CDR and adaptive equalizer are 15.1 mW and 6.8 mW. The chip area is 1.38 mm2 and the core area is 0.13 mm2.

    摘要 i Abstract ii 誌謝 iii 目錄 iv 圖目錄 x 表目錄 xviii 第1章 緒論 1 1.1 研究動機 1 1.2 論文架構 5 第2章 高速串列傳輸之訊號完整性 7 2.1 基本觀念 7 2.1.1 隨機二元資料的特性 7 2.1.2 資料編排形式 9 2.1.3 單一位元脈衝響應與等化器之關係 10 2.2 傳輸線理論 13 2.3 相位雜訊理論 18 2.4 時脈抖動簡介 23 2.4.1 隨機性抖動(RJ) 24 2.4.2 定量性抖動(DJ) 25 2.4.2.1 資料相關抖動(DDJ) 25 2.4.2.2 責任週期失真(DCD) 26 2.4.2.3 週期性抖動(PJ) 27 2.4.3 抖動量測的方法 28 2.4.3.1 時間間隔誤差(Time Interval Error, TIE) 29 2.4.3.2 週期抖動(Period Jitter) 30 2.4.3.3 循環抖動(Cycle-to-Cycle Jitter, C2C Jitter) 31 2.4.3.4 三種抖動量測方式之差別 32 2.5 眼圖分析 33 2.6 誤碼率 34 第3章 時脈與資料回復電路和等化器之背景簡介 37 3.1 時脈與資料回復電路簡介 37 3.1.1 資料型態 38 3.1.2 相位偵測器型態 39 3.1.3 取樣速率 40 3.1.4 抖動轉移函數 41 3.1.5 抖動容忍度 42 3.2 傳統時脈與資料回復電路 43 3.2.1 鎖相迴路式時脈與資料回復電路 43 3.2.2 混合鎖相迴路/延遲鎖相迴路式資料與時脈回復電路 45 3.2.3 超取樣式時脈與資料回復電路 46 3.2.4 相位選擇式時脈與資料回復電路 47 3.3 等化器電路簡介 48 3.3.1 等化器的補償狀態 48 3.3.2 等化器的種類 51 3.3.3 自適應機制的種類 53 3.4 傳統連續時間線性等化器電路 57 3.4.1 雙路徑回授控制之自適應等化器 57 3.4.2 頻譜平衡技術之自適應等化器 58 3.4.3 結合資料與時脈電路之自適應等化器 59 3.4.4 利用斜率偵測技術之自適應等化器 60 3.5 比較與討論 61 第4章 具自適應等化器之資料與時脈回復電路設計與實現 63 4.1 電路架構 63 4.2 操作說明 65 4.2.1 在具有符碼間干擾之狀態下資料與時脈回復電路之鎖定情況 65 4.2.2 符碼間干擾偵測器分析 66 4.2.2.1 探討ISIUP之行為 68 4.2.2.2 探討ISIDN之行為 71 4.2.2.3 利用符碼間干擾偵測器實現之自適應等化器迴路 75 4.3 系統分析 77 4.3.1 頻率資訊鎖相迴路系統分析 77 4.3.2 時脈與資料回電路系統分析 80 4.3.3 以符碼間干擾偵測技術實現自適應等化器之系統分析 88 4.4 行為模擬 91 4.5 子電路介紹 93 4.5.1 符碼間干擾偵測電路 93 4.5.2 利用電流放大技術之迴路濾波器 96 4.5.3 混合式之半速率二進相位偵測器 97 4.5.4 相位頻率偵測器 100 4.5.5 電荷幫浦 101 4.5.6 電壓控制震盪器 103 4.5.7 連續時間線性等化器 105 4.5.8 除頻器 106 4.5.9 擺幅轉換電路 107 4.6 模擬結果 109 4.6.1 通道模型 109 4.6.2 操作在2.5 GHz之鎖相迴路模擬 111 4.6.2.1 佈局前模擬 111 4.6.2.2 佈局後模擬 112 4.6.2.3 閉迴路相位雜訊模擬 114 4.6.3 具自適應等化器之5 Gbps資料與時脈回復電路模擬 115 4.6.3.1 佈局前模擬 115 4.6.3.1.1 長通道模擬 116 4.6.3.1.2 短通道模擬 117 4.6.3.2 佈局後模擬 118 4.6.3.2.1 長通道模擬 120 4.6.3.2.1 短通道模擬 121 4.6.4 抖動容忍度模擬 122 4.6.5 結果整理 124 4.6.5.1 操作在2.5 GHz之鎖相迴路模擬 124 4.6.5.2 具自適應等化器之5 Gbps資料與時脈回復電路模擬 125 第5章 晶片佈局與量測 129 5.1 電路佈局 129 5.1.1 晶片封裝 130 5.1.2 佈局規劃與電源規劃 132 5.2 量測考量 133 5.2.1 量測環境 133 5.2.2 印刷電路板 134 5.2.3 高頻輸出緩衝器 135 5.2.4 低頻輸出緩衝器 138 5.2.5 高頻輸入端 139 5.3 晶片與印刷電路板照相 141 5.4 量測結果 142 5.4.1 頻率資訊鎖相迴路量測 142 5.4.2 等化器量測 145 5.4.3 資料與時脈回復電路量測 146 5.4.4 具自適應等化器之資料與時脈回復電路量測 149 5.4.5 抖動容忍度量測 156 5.5 規格比較表 162 第6章 結論 165 6.1 結論 165 6.2 未來研究方向 166 6.2.1 抵銷隨機偏移 166 6.2.2 控制機制數位化 166 參考文獻 167

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