本論文利用選擇性氧化複晶矽鍺奈米柱/氮化矽/矽基材結構來成長製作一體成型之鍺量子點/二氧化矽/矽的金氧半異質結構。此量子點的形成是利用矽鍺氧化優先將矽氧化生成二氧化矽且析出鍺再匯聚而成。所形成的鍺量子點進一步催化鄰近氮化矽的局部氧化，進而鑽入並穿透氮化矽碰觸到矽基板。在此同時，鍺量子點的外圍披覆有一層4 nm厚的二氧化矽，並有一約3-5 nm之矽鍺層穿透此二氧化矽滲入下方矽基板之表面，形成一體成型之鍺量子點/二氧化矽/矽的金氧半異質結構。由於此二氧化矽是由矽在高溫下熱氧化所生成，因此有很好的矽鍺/二氧化矽介面特性，可作為矽鍺的閘介電層。而且此薄薄的二氧化矽可以有效地舒緩鍺量子點與矽之間的晶格失配，形成品質良好的鍺/二氧化矽/矽金氧半異質接面。
透過變溫高低頻之電容-電壓量測分析，吾人可萃取出鍺量子點與二氧化矽之介面缺陷密度約2×1011　cm-2eV-1 ，足以佐證本文所提出之鍺/二氧化矽/矽的介面具有元件等級的介面品質。另外，對直徑大小約75-90 nm的鍺量子點進行拉曼量測分析，可清楚觀察到較小的鍺量子點感受到周圍介質所施予更大的壓縮應力。進一步計算分析可知，當鍺量子點鑽入矽基板內的體積比例愈大，受到氮化矽與矽介層的壓縮應力影響愈高，與實驗觀察結果相符。由此可知，本文所提出之一體成型之鍺量子點/二氧化矽/矽的金氧半異質結構不僅可以同時得到Ge/Si與Ge/SiO2良好的介面，更可以透過調變鍺量子點的大小尺寸與鑽入矽基板的深度來進行鍺量子點的介面應力工程化，非常有利於日後鍺金氧半電晶體之製作。

In this thesis, we demonstrated a novel method for the fabrication of a designer Ge quantum dot (QD)/SiO2/Si heterostructure by selectively oxidizing poly-Si0.83Ge0.17 nano-pillars over buffer layers of Si3N4 that were deposited over Si substrates. The formation of Ge QDs was realized by thermally oxidizing the SiGe pillar through the preferential oxidation of Si, the segregation of released Ge to be incorporated within the as-yet unoxidized SiGe grains, and ultimately the Ostwald ripening of the Ge QD. Attendant to the formation of Ge QDs, catalytically-enhanced local oxidation of Si3N4 by Ge QD itself also facilitates the QD penetration through Si3N4, ultimately leading to the QDs in contact with the underlying Si substrate. An approximately 4-nm-thick interfacial layer of oxide was observed at the interface of Ge QD/Si substrate in conjunction with the presence of a 3-5 nm SiGe intermixing shell at the interface of Si substrate, generating a self-organized Ge QD/SiO2/Si heterostructure. Thereby we are able to not only create an entirely new heterostructure interface with the Si substrate, but also grow superior SiO2 directly over Ge.
Ge QD experiences compressive strain from the Si substrate, and Raman characterization reveals that the compressive stress is much enhanced with a reduction in the QD size. The interfacial quality of the Ge QD/SiO2/Si heterstructure is further characterized on a metal-oxide-semiconductor (MOS) diode. The extracted interface trap density (Dit) from temperature-dependent high- and low-frequency capacitance-voltage (C-V) characteristics was about 2×1011　cm-2eV-1, indicating the high quality of the SiO2/Ge QD interface being favorable for the realization of Ge MOS devices with good oxide integrity.

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