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研究生: 葉宗諺
Tsung-Yen Yeh
論文名稱: 應用於物聯網之低複雜度空間調變收發機設計與實現
Design and Implementation of a Low-complexity Spatial Modulation Transceiver for Internet of Things
指導教授: 蔡佩芸
Pei-Yun Tsai
口試委員:
學位類別: 碩士
Master
系所名稱: 資訊電機學院 - 電機工程學系
Department of Electrical Engineering
論文出版年: 2018
畢業學年度: 106
語文別: 中文
論文頁數: 96
中文關鍵詞: 物聯網空間調變收發機
外文關鍵詞: IoT, Spatial Modulation, Transceiver
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  • IoT(Internet of Things)的應用日趨變多,如智慧家庭、遠距照護、智慧城市等,而符合其應用的特性是要低功耗,長距離傳輸的特點。低功耗是為了解決充電不易或是增加電池壽命。長距離傳輸是讓感應器(sensor)可以分布更廣,加大應用可能性。此論文的無線通訊收發機,是在IEEE 802.15.4的規範下設計封包形式,使用了空間調變(spatial modulation),增加了頻譜效率(spectral efficiency)但又不增加射頻前端的複雜度。考慮的效應有多重路徑衰減,載波頻率偏移(CFO)和雜訊(AWGN)。接收機的功能區塊分成三大塊。首先是粗略同步,使用了前置序列的特性來偵測邊界且同時估測了CFO的初始相位,硬體部分將閒置運算的硬體重複使用,使得CORDIC、乘法器和延遲器的個數減少33%。接著是精確補償,進一步修正且同時補償相位,亦為多天線模式做了通道估測且具有持續的殘餘相位的補償功能,在硬體的部分也將閒置的硬體重複利用,使得CORDIC和乘法器的個數減少67%,而查表大小,也利用對稱性和重複性來降低表的大小,讓查表的使用位元數減少75%。最後一塊是資料還原,在多天線模式下使用最大似然偵測(maximum likelihood detection)來偵測OQPSK的空間調變訊號,而其硬體的實現由演算法化簡與分類重複運算,不需用乘法器即可完成運算,在比較器的部分利用延遲(latency)和資料分組,使得比較器使用數量減少73%。以上利用定點數模擬的結果,來完成硬體,根據合成結果,操作時脈最快可達7.594 MHz,使得傳輸速度滿足3Mbps需求。


    This thesis presents an O-QPSK transceiver with 2×2 spatial modulation for Internet of Things applications. The communication system uses 2.4GHz carrier frequency with a 3Mbps data rate. The transceiver uses 2×2 MIMO transmission with spatial modulation. The receiver is separated into three main blocks, including coarse synchronization, fine synchronization and data recovery.
    First, for coarse synchronization, we decrease the usage of hardware such as CORDICs, multipliers, and DFFs about 33% to achieve symbol boundary detection. Then, for the fine synchronization, we have phase compensation, residual phase tracking to compensate received signals and channel estimation for data recovery. We also reuse the hardware, like CORDICs and multipliers, so about 67% hardware is reduced. As for the look up table, we take advantage of the symmetry and repetition so that our table size is reduced by 75%. Last but not least, for the data recovery block, maximum likelihood detection is used for recovering signal. By simplifying our algorithm, we adopt no multiplier in this block. Due to the trade-off between the number of comparators and latency, we can eliminate the comparators by 73%. According to the synthesis result, the maximum clock frequency is 7.594 MHz and the implementation can achieve the data rate of 3Mbps.

    目錄 目錄 ii 圖目錄 iv 表目錄 vi 第一章 緒論 1 1.1 簡介與研究動機(Motivation) 1 1.2 論文組織(Organization) 3 第二章 發送機架構與通道效應 4 2.1 系統特性介紹(System Description) :空間調變(Spatial Modulation , SM) 4 2.2 系統規格(System Specification) 6 2.3 封包格式設計(Packet Formation) 7 2.4 發送機架構(Transmitter Architecture) 9 2.4.1 位元與符元對應(Bit-To-Symbol Mapping) 9 2.4.2 串列轉並列(Serial-To-Parallel) 9 2.4.3 符元與子碼對應(Symbol-To-Chip Mapping) 10 2.4.4 O-QPSK 調變(O-QPSK Modulation) 10 2.4.5 脈波塑型(Pulse Shaping) 11 2.5 考慮效應及通道模型(Channel Model and Effect) 15 第三章 接收機演算法 16 3.1封包偵測與粗略同步(Packet Detection and Coarse Synchronization) 17 3.1.1傳統延遲相關性(Conventional Delay-and-Correlation) 17 3.1.2改良延遲相關性(Modified Delay-and-Correlation) 19 3.1.3符元邊界偵測(Symbol Boundary Detection) 20 3.1.4載波頻率偏移估測(CFO Estimation) 23 3.2精確同步(Fine Synchronization) 25 3.2.1初始相位差估測(Initial Phase Offset Estimation) 25 3.2.2 CFO估測誤差偵測(CFO Estimation Error Detection) 26 3.2.3殘餘相位誤差追蹤(Residual Phase Error Tracking) 28 3.3通道估測(Channel Estimation) 31 3.4 資料回復 – 空間調變偵測(Data Recovery – SM Detection) 32 3.5 系統效能模擬(System Performance Simulation) 36 第四章 接收機硬體架構 37 4.1 接收機架構圖與定點數規格 38 4.2 粗略同步(Coarse Synchronization)-相關硬體與架構 39 4.2.1傳統延遲相關器(Conventional Delay Correlator) 39 4.2.2 改良延遲相關器(Modified Delay-and-Correlator) 40 4.2.3 指標式延遲緩衝器(Pointer Based Delay Buffer) 41 4.2.4 坐標軸旋轉數位計數器(CORDIC) 42 4.2.5 共享粗略同步延遲相關器 44 4.2.6 邊界偵測(Boundary Detection) 45 4.2.7 載波頻率偏移估測(CFO Estimation) 47 4.2.8 粗略同步硬體化簡(Coarse Synchronization Hardware Reduction) 49 4.3 精確同步(Fine Synchronization)-相關硬體與架構 50 4.3.1 相位補償(Phase Compensation) 51 4.3.2 相位差計算(Phase Difference Computation) 52 4.3.3 弦波振幅產生器(Sine/Cosine Wave Generator) 53 4.3.4 精確同步硬體化簡(Fine Synchronization Hardware Reduction) 55 4.4 資料回復(Data Recovery)-相關硬體與架構 56 4.4.1空間調變偵測(SM detection) 56 4.4.2比較器(Comparator) 71 4.4.3資料回復硬體化簡(Data Recovery Hardware Reduction) 74 4.5 系統效能模擬圖-定點數(System Performance Simulation-Fixed Point) 75 4.6 硬體合成結果與模擬波型圖 77 第五章 結論 81 參考文獻 82

    參考文獻
    [1] IEEE Standard for Local and Metropolitan Area Networks Part 15.4:Low-Rate Wireless Personal Area Networks(LR-WPANs),IEEE Computer Society Std.
    [2] Rashmi-Sharan Sinha, Yi-qiao Wei, Seung-Hoon Hwang.” A survey on LPWA technology: LoRa and NB-IoT”, Division of Electronics and Electrical Engineering, Dong guk University-Seoul, Republic of Korea, 21 March 2017
    [3] Jin-Seong Lee and Jai-Yong Lee.” Prediction-Based Energy Saving Mechanism in 3GPP NB-IoT Networks”, School of Electrical and Electronics Engineering, Yonsei University, Published online Sep 1 2017
    [4] Ron Porat, ” NEXT GEN WIFI: EVOLUTION BEYOND 11AC “, Broadcom corporation, 2012.
    [5] M. Di Renzo, H. Hass, A. Ghrayeb, et al., “Spatial Modulation for Generalized MIMO: challenges, opportunities, and implementation”, Proc. IEEE, vol.102, no. 1, pp.56-103, Jan 2014
    [6] Ching-Hao Yang and Pei-Yun Tsai, “Design of a low-complexity O-QPSK transceiver with spatial modulation for internet-of-things applications”,IEEE Asia Pacific Conference on Circuits and Systems (APCCAS), 2016
    [7] K. H. Chen and H. P. Ma, “A Low Power ZigBee Baseband Processor,” in Proc. of International SOC Conference, Nov. 2008 pp. 40-43.
    [8]Ze-Mu Chang, “Design and Evaluation of Gigabit Indoor Wireless Communication Systems”, M.S. thesis, National Central University, Taoyuan, Taiwan, 2010
    [9] Ching-Hao Yang, “Design of a Multi-mode Low-complexity Transceiver for Wireless Sensor Networks”, M.S. thesis, National Central University, Taoyuan, Taiwan, 2015 pp.40-41.
    [10] Kuan-yuen Liao, “The Baseband Signal Processing and Circuit Design for 915 MHz Amplitude Shift Keying Modulation Mode of the IEEE 802.15.4 – 2006 Low Rate-Wireless Personal Area Network”, M.S. thesis, National Sun Yet-San University, Kaoshung, Taiwan, 2009
    [11] N. Serafimovski, and et al., “Practical Implementation of Spatial Modulation,” IEEE Transactions on Vehilcular Technology, pp. 4511~4523, Nov. 2013.
    [12] Ching-Hao Yang, “Design of a Multi-mode Low-complexity Transceiver for Wireless Sensor Networks”, M.S. thesis, National Central University, Taoyuan, Taiwan, 2015 pp.76-87.

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