本論文利用TSMC 0.18-?m CMOS製程設計功率放大器，在設計上分成兩部份，第一部份為以全積體化CMOS功率放大器為目標，使用功率結合技術，設計三個高功率輸出功率放大器，而第二部份功率放大器則是以高效率為設計方向，架構以反E類為主。
各電路特性量測如下：採用功率結合變壓器技術之功率放大器，增益量測為13.6 dB，輸入回返損耗約為10.6 dB，輸出回返損耗約為6.42 dB，1-dB增益壓縮點輸出功率為25.8 dBm，效率為17.2 %；Figure 8功率結合變壓器之功率放大器，增益量測結果為14.2 dB，輸入回返損耗約為20.4 dB，輸出回返損耗約為3.2 dB，1-dB增益壓縮點輸出功率為24.2 dBm，效率為14.7 %；雙級功率結合技術功率放大器，增益量測結果為19.1 dB，輸入回返損耗約為15.7 dB，輸出回返損耗約為7.7 dB，1-dB增益壓縮點輸出功率為12.3 dBm，飽和輸出功率為22.7 dBm，效率為9.1 %；反E類功率放大器，增益量測結果為19.4 dB，輸入回返損耗約為12.5 dB，輸出回返損耗約為2.66 dB，1-dB增益壓縮點輸出功率為20.8 dBm，效率為30.4 %。

This thesis presents CMOS power amplifier (PA) implemented in 0.18 ?m CMOS technology. The implemented circuits include two PA categories. The first category is target for the fully integrated CMOS PA design, three power amplifiers using power-combining transformer are presented, The second category is target for high-efficiency power amplifier which is based on the 反E類 switch technique.
The measured results are summarized as below, the PA with power-combining transformer technique achieves a power gain of 13.6 dB with input and output return losses of 10.6 dB and 6.42 dB, a 1-dB gain compression point (P1dB) of 25.8 dBm, a power added efficiency (PAE) at P1dB of 17.2 %. The PA with figure 8 power-combining transformer achieves a power gain of 14.2 dB with input return and output return losses of 20.4 dB and 3.2 dB, a P1dB of 24.2 dBm, a PAE at P1dB of 14.7 %. The PA with two stage power-combining technique achieves a power gain of 19.1 dB with input and output return losses better than 15.7 dB and 7.7 dB, a P1dB of 12.3 dBm, a saturation power of 22.7 dBm, a maximum PAE of 9.1%. The PA with inverse class E achieves a power gain of 19.4 dB with input and output return loss of 12.5 dB, and 2.66 dB, a P1dB of 20.8 dBm, a PAE at P1dB of 30.4 %.

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