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研究生： 黃繼賢
Mars Huang
論文名稱： 應用於數位視頻廣播系統之頻率合成器及3.1Ghz寬頻壓控震盪器
Design of Frequency Synthesizer with 3.1 GHz Wide-Tuned LC-VCO for DVB-T/H/C System
指導教授： 薛木添
Muh-Tian Shiue
口試委員:
學位類別： 碩士
Master
系所名稱： 資訊電機學院 - 電機工程學系
Department of Electrical Engineering
畢業學年度： 95
語文別： 英文
論文頁數： 55
中文關鍵詞： 壓控震盪器 、頻率合成器
外文關鍵詞： Frequency Synthesizer, VCO, PLL
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    • 近年來，頻率合成器在現代的通訊系統上扮演著很重要的角色。在這本論文中，我們主要是在研究有關於頻率合成器與視頻廣播系統 DVB-T/H/C 系統上的關連。因此在這方面，我們希望能夠針對視頻廣播系統 DVB-T/H/C 觀點需求並且實現頻率合成器對其系統上的應用。除此之外，我們也會發現壓控震盪器在頻率合成器裡是很重要的電路元件。最主要是因為壓控震盪器的效能將會直接影響到頻率合成器的運作正確性。而在壓控震盪器的設計上我們主要是以3.1 GHz為此電路的中心頻率且採用 TSMC 0.18μm 1P6M CMOS 的製程技術。而此壓控振盪器可以達到 26.5% 的調頻範圍，相為雜訊可達到 -123dBc @ 1 MHz，-100dBc @ 100 kHz。供應電壓為1.1Volt。此電路設計的優點主要是他可以有效的降低相位雜訊，節省功率消耗且達到較寬的調頻範圍。
    而頻率合成器主要是以鎖相迴路為基礎所延伸的一種電路。而鎖相迴路設計上的最大挑戰不外乎低抖動 (low jitter)，快速鎖定，以及功率消耗的問題。所以我們希望利用上述之壓控振盪器能設計出寬頻，低抖動雜訊，低功率消耗和快速鎖定且能應用於視頻廣播系統 DVB-T/H/C之頻率合成器。

    Recently, frequency synthesizer plays an important role in modern communication. In
    this thesis, we study about the theory of frequency synthesizer in connection with DVB-T/H/C
    system. Therefore, we hope realize this application in the light of contribution in DVB-T/H/C.
    Besides, VCO is the major component in frequency synthesizer. The performance of the VCO
    would directly effect on properties of frequency synthesizer. A 3.1GHz LC VCO is designed
    in TSMC 0.18 µm standard CMOS process which achieves a very wide tuning range of 26.5%
    and simulated phase noise of -123dBc at a 1MHz and -100dBc at a 100kHz offset in a 3.1GHz
    operated carrier, while drawing 1mA from a 1.1 V supply voltage. The advantage of this design
    reveals that it can effectively reduce the phase noise and save power consumption together with
    the chip area. In addition, it also makes the LC-VCO to achieve a wide tuning range. Generally,
    this design also can meet the demand of the DVB-T/H/C system.
    Frequency synthesizer design is based on PLL. The challenge in designing the frequency
    synthesizer is the improvement of the performance like jitter, locking time, and power consumption.
    In our target, we hope design a wide band, low jitter, low power consumption ,and fast
    locking frequency synthesizer for DVB-T/H/C system.

    Abstract ii List of Tables v List of Figures vi Chapter 1 Introduction 1 1.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 1.2 Motivation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 Chapter 2 The Concept Of Frequency Synthesizer 5 2.1 The Frequency Synthesizer Background Theory . . . . . . . . . . . . . . . . . . . 5 2.2 The Component Of Frequency Synthesizer . . . . . . . . . . . . . . . . . . . . . . 6 2.2.1 Phase Frequency Detector (PFD) . . . . . . . . . . . . . . . . . . . . . . . 6 2.2.2 Charge Pump (CP) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 2.2.3 Loop Filter (LF) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 2.2.4 Voltage-Controlled Oscillator (VCO) . . . . . . . . . . . . . . . . . . . . . 11 2.2.5 Frequency Divider (FD) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 2.3 High Performance PLL Examples . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 2.3.1 A Low-Power Adaptive Bandwidth PLL and Clock Buffer With Supply- Noise Compensation [19] . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 2.3.2 Self-Biased High-Bandwidth Low-Jitter 1-to-4096 Multiplier Clock Generator PLL [23] . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 2.4 The PLL Design For Frequency Synthesizer . . . . . . . . . . . . . . . . . . . . . 17 2.4.1 The Linear Model Of PLL . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 2.4.2 Third Order PLL Model . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 2.4.3 PLL Behavioral Model Simulation . . . . . . . . . . . . . . . . . . . . . . 21 Chapter 3 3.1 GHz Wide-Band VCO 23 3.1 Circuit Design . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 3.2 The Switched Tuning Design . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 Chapter 4 3.1 GHz Wide-tuned LC-VCO Pre-Simulation, Layout And Measurement 30 4.1 Decision Of The Component Size . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 4.2 The VCO Performance And Pre-Simulation Result . . . . . . . . . . . . . . . . . 33 4.3 Layout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 4.4 3.1GHz Wide-Tuned LC-VCO Measurement Result . . . . . . . . . . . . . . . . . 38 Chapter 5 The Integer N Frequency Synthesizer Pre-Simulation Result 43 5.1 Architecture Of The Proposed Frequency Synthesizer . . . . . . . . . . . . . . . . 43 5.2 Phase Frequency Detector (PFD) . . . . . . . . . . . . . . . . . . . . . . . . . . . 44 5.3 Charge Pump (CP) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45 5.4 Programmable Divider . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47 5.5 Current Mode Logic (CML) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49 5.6 Frequency Synthesizer Simulation Results . . . . . . . . . . . . . . . . . . . . . . 51 Chapter 6 Conclusion and future work 52 Bibliography 54

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