跳到主要內容

簡易檢索 / 詳目顯示

研究生: 游金龍
Jin-long You
論文名稱: 一種用於電阻串陣列的平衡寄生電阻通道繞線法
BICR: A Balanced Interconnect Channel Routing Scheme for a Resistor-String Array
指導教授: 陳竹一
Jwu-e Chen
口試委員:
學位類別: 碩士
Master
系所名稱: 資訊電機學院 - 電機工程學系
Department of Electrical Engineering
畢業學年度: 98
語文別: 中文
論文頁數: 41
中文關鍵詞: 電阻串陣列空間相關性平衡導線通道繞線法
外文關鍵詞: spatial correlation, Balanced Interconnect Channel Routing, resistor-string array
相關次數: 點閱:8下載:0
分享至:
查詢本校圖書館目錄 查詢臺灣博碩士論文知識加值系統 勘誤回報
  • 本論文利用電阻串陣列來排列探討空間相關性與元件分段其抑制非線性誤差的能力,而隨著改變排列所造成在實體佈局上繞線困難度增加,且導線阻值不一致會增加系統失誤,增加積分非線性誤差。利用本論文提出佈局上平衡導線通道繞線法的四個準則:相同的via 個數、垂直方向的金屬層阻值相同且水平方向的金屬層阻值相同、最佳聯線路徑、依導線長度調整其寬度,便能在同位元不同排列下,平衡所有導線寄生阻值。在四位元探戈行軍式螺旋排法,導線寬1.42μm 使用平衡導線通道繞線法,可以將整體導線阻值的均方根誤差從1.89Ω減少到0Ω。


    This paper discusses the suppression capability of INL with the concept of spatial correlation and segment method in the resistor-string array. In physical layout, permutation may cause the difficulty in routing, systematic error like unbalanced channel resistance increases the INL. This paper proposes four rules on physical routing called Balanced Interconnect Channel Routing (BICR), adjusting the channel width follow the channel length, choosing the same via numbers, the metal resistances of vertical direction are the same and the metal resistances of horizontal direction are the same too, and optimizing the path of interconnection to balance the parasitic resistances in all channel under different permutation of the same resolution. In 4bits Snake sequence of Tango Route March, the root-mean-square value of parasitic resistance can be reduced from 1.89 ohm to zero ohm by BICR when the width of metal line in interconnect is 1.42um.

    摘要i Abstractii 誌謝iii 目錄iv 圖目錄vi 表目錄viii 第一章 簡介1 1.1 前言1 1.2 論文組織2 第二章 數位/類比轉換器規格分析3 2.1 數位/類比轉換器簡介3 2.2 數位/類比轉換器靜態特性分析4 2.2.1 微分非線性誤差4 2.2.2 積分非線性誤差5 2.3 電阻串聯式6 第三章 空間相關性與模擬方式8 3.1 空間相關性8 3.2 不匹配的原因10 3.3 不匹配與空間相關性10 3.4 數位/類比轉換器靜態特性模擬11 3.5 排列的探討12 3.5.1 Tango 排法12 3.5.2 Tango_Route March14 3.5.3 其他排列15 3.5.4 模擬結果17 第四章 元件的分段與繞線的匹配19 4.1 元件的分段19 4.1.1 分段的聯接19 4.1.2 分段的排法21 4.1.3 區域繞線與全域繞線24 4.2 繞線的匹配26 4.2.1 電阻與寄生電阻26 4.2.2 導線電阻的計算29 4.2.3 導線電阻匹配方法29 4.2.4 模擬結果34 第五章 結論39 參考文獻40

    [1] C. S. G. Conroy, W. A. Lane, and M. A. Moran,“Statistical Design Techniques for
    D/A Converters,” IEEE JOURNAL OF SOLID-STATE CIRCUITS, vol. 24, no. 4.pp. 1118-1127, Aug. 1989.
    [2] J. Xiong, V. Zolotov, and L. He, “Robust Extraction of Spatial Correlation,”International Symposium on Physical Design, pp. 619-630, Apr. 2006.
    [3]C. Shi, J. Wilson, and M. Isamail, “Design Techniques for Improving Intrinsic Accuracy of Resistor String DAC’s,” IEEE International Symposium on Circuits and Systems, vol. 1, pp.400-403, May 2001.
    [4]P. E. Allen and D. R. Holberg, CMOS Analog Circuit Design, 2nd Ed. New York:Oxford, 2002.
    [5]藍東鑫, “元件匹配特性在空間上的相關分析,” 中華大學電機工程學系碩士論文, 2002.
    [6] R. Behzad, Design of Analog CMOS Integrated Circuits, New York: Mc-Graw Hill Inc., 2001.
    [7] A. Hastings and R. A. Hastings, The Art of Analog Layout, Prentice Hall, 2000.
    [8] M. J. M. Pelgrom, A. C. J. Duinmaijer, and A. P. G. Welbers, “Matching Properties of MOS Transistors,” IEEE Journal of Solid-state Circuits, vol. SC-24, pp.1433-1439, Oct. 1989.
    [9]林智勝, “Tango_RM:一個電阻串聯連續參考值產生之強化排列結構,” 中華大學電機工程學系碩士論文, 2004.
    [10]J. Deveugele, G. V. d. Plas, M. Steyaert, and W. Sansen, “A Gradient Error and Edge Effect Tolerant Switching Scheme for a High Accuracy DAC,” IEEE Transactions on Circuits and Systems I, vol. 51, no. 1, pp. 191-195, Jan. 2004.
    [11]G. V. d. Plas, J. Vandenbussche, W. Sansen, M. S. J. Steyaert and G. G. E. Gilen, ”A 14-bit Intrinsic Accuracy Q^2 Random Walk CMOS DAC,“ IEEE J. Solid-State Circuits, vol. 34, no. 12, pp.1708-1718, Dec. 1999.
    [12]莊勝富, “電阻串聯式連續參考值產生器的佈局,” 中央大學電機工程學系碩士論文, 2007.
    [13] Cadence Design Systems, SKILL Language Reference, Nov. 2002.

    QR CODE
    :::