這個可參數化的數位訊號處理器有不同獨立的參數可以設定。我們更進一步地加入一些特殊應用於通訊系統的電路給使用者選用。我們把這一種處理器稱為可參數化融合特殊應用於數位訊號基礎的處理器 ( parameterized ASIC/DSP processor )。除了特殊應用的電路外，為了增強整體的效能，我們加入高度平行化的架構稱之為雙 MAC 架構。最後，為了減少功率消耗，我們也應用了一個低功率的 MAC 單元在這顆數位訊號處理器裡。

The proposed DSP processor itself is a parameterized core with several independent parameters. Furthermore, a better concept is to combine some special-purposed circuits in the parameterized DSP core for option. And we term this kind processor as parameterized ASIC/DSP processor. In addition to the special-purposed circuits, the highly degree parallelism architecture ( Dual MAC ) is used in the processor to upgrade its performance. In order to reduce the power consumption, a low power MAC unit is used in the DSP

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