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研究生： 蔡皓州
Hao-Chou Tsai
論文名稱： 使用空間相關性分析來探討共質心線段式佈局在運算放器的影響
Spatial Correlation Analysis of Common-Centroid Layout Placement for an OpAmp
指導教授： 陳竹一
Jwu-e Chen
口試委員:
學位類別： 碩士
Master
系所名稱： 資訊電機學院 - 電機工程學系
Department of Electrical Engineering
畢業學年度： 96
語文別： 中文
論文頁數： 51
中文關鍵詞： 空間相關性
外文關鍵詞： Spatial Correlation
相關次數： 點閱：16  下載：0 
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    • 電晶體進入奈米尺寸帶來製程漂移、參數劇烈變動，導致良率更難以評估。在SPICE電路模擬分析時，往往將元件參數彼此間的變動視為獨立的；然而電路在晶圓廠製造過程中，元件彼此間的參數變動是有關聯性的。所以，加入相關性概念的電路模擬更能客觀與準確預測電路特性。因為在實際佈局上，常運用多線段電晶體的擺放來降低不匹配效應。故本論文導入相關性變動探討多線段電晶體對雙級放大器的影響。並觀察Common-Centroid佈局抑制參數變動的效果。最後提出一種方法來排除大量元件模擬上的限制。

    While the critical dimension of transistors gets in advancement to nano-meter, it will bring the drift for larger parameter variability in manufacturing process, and is more difficult to evaluate the yield. In SPICE simulation, it treats the parameter for each same-type device as identical. Therefore we could not know the mismatch between devices. However, the parameter variation of each device should have certain correlation during manufacturing process. Taking the correlation into the simulation, it would be more objective and accurate for predicting the circuit performance.
    Segments of devices are widely used in physical implementation for reducing the mismatch. A two-stage OPA is used to analyze the effect of device correlation and it is observed that how the mismatch is suppressed in Common-Centroid layout.

    摘要………………………………………………………………….Ι Abstract……………………………………………………………...Ⅱ 致謝………………………………………………………………….Ⅲ 目錄………………………………………………………………….Ⅳ 圖目錄……………………………………………………………….Ⅶ 表目錄……………………………………………………………….Ⅹ 第一章 簡介………………………………………………………...1 第二章 前置作業…………………………………………………...3 2-1 統計量相關名詞定義……………………………………………3 2-1-1 母體(Population)………………………………………..3 2-1-2 樣本(Sample)……………………………………………3 2-1-3 平均值(Mean)…………………………………………..3 2-1-4 變異數(Variance)………………………………………..3 2-1-5 標準差(Standard Deviation……………………………..4 2-1-6 共變異數(Covariance, σxy)…………………………..4 2-1-7 相關係數(Correlation coefficient, ρ)………………....5 2-1-8 常態分佈(Normal distribution) ………………………...5 2-1-9 蒙地卡羅分析…………………………………………..7 2-2 不匹配參數……………………………………………………...8 第三章 空間相關性………………………………………………...11 3-1 Pelgrom’s Model ………………………………………...11 3-2 一維的空間相關性………………………………………13 3-2 二維的空間相關性………………………………………14 第四章 實驗流程…………………………………………………...15 4-1 模擬流程…………………………………………………..15 4-1-1 臨限電壓VT0的平均值…………………………19 4-1-2 臨限電壓VT0的標準差…………………………20 4-1-3 臨限電壓VT0的相關係數矩陣…………………21 4-1-4 修改原始電路檔…………………………………24 4-2 模擬結果…………………………………………………..26 4-2-1 在不同相關性下對電路效能的影響……………27 4-2-2 最佳佈局排法……………………………………28 4-2-3 最差佈局排法……………………………………29 第五章 Common-Centroid線段式佈局及實驗結果……………..33 5-1 分段排法………………………………………………..33 5-2 Common-Centroid線段式佈局………………………….35 5-3 指令.data的限制…………………………………….......38 5-4 改善方式…………………………………………………39 5-5 線段式佈局模擬結果……………………………………41 第六章 結論……………………………………………...…………49 參考文獻…………………………………………………………….50

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