本論文研究主軸為以懸置帶線架構實現準集總元件組成的雙工器，透過系統化的流程，依序設計組成雙工器的高、低通濾波器，逐步加入電路佈局中的高頻寄生效應、實做環境考量，與製程變異分析，而完成雙工器的設計。
論文首先介紹以高、低通濾波器組成理想雙工器之工作原理。並且針對高、低通濾波器於懸置帶線架構的電路佈局設計時產生的寄生效應進行分析，再建立考量寄生效應的修正電路模型，並由網路參數運算的方式建立高低、通濾波器中準集總元件的萃取公式。藉以於電路模擬軟體的輔助下判斷修改元件值的設計方向。
接續則提出系統化的雙工器設計方法，建立雙工器的設計，並且分別以五階與七階的雙工器實際設計範例演示設計流程。再納入量測時所須要的SMA接頭至懸置帶線轉接器設計，以及金屬外罩於製做時產生的圓孔與預留空間等實做考量於設計中，逐步完成所訂規格下的雙工器設計。最後針對製程變異進行評估，透過變異分析判斷實際製做時能夠容許的誤差範圍並且確保電路成品能夠與模擬吻合。本研究所提出之五階雙工器的量測結果，高通頻帶內植入損耗最大為為0.96 dB，低通頻帶內植入損耗最大為0.94 dB，低通與高通植入損耗響應交錯頻率15.25 GHz的植入損耗為3.8 dB，高通路徑的止帶衰減於0.8倍交錯頻率處可達39.6 dB，低通路徑的止帶衰減於1.2倍交錯頻率處達15 dB。反射損耗的部份，高通埠反射損耗於18.2-24.5 GHz均可大於13.1 dB，低通埠反射損耗於DC-14.46 GHz均可大於16.3 dB，共同埠反射損耗於DC-24.5 GHz均大於12.4 dB。電路之平面面積約為9.1×21.7 mm2( )，整體外部體積大小為21.7×18.0×22.3 mm3( )。而七階雙工器的量測方面結果，高通頻帶內植入損耗為1.25 dB，低通頻帶內植入損耗為1.22 dB，低通與高通植入損耗響應交錯頻率11.4 GHz的植入損耗為4.36 dB，高通路徑的止帶衰減於0.8倍交錯頻率處可達42.1 dB，低通路徑的止帶衰減於1.2倍交錯頻率處達36.3 dB。反射損耗的部份，高通埠反設損耗於12.1-18.2 GHz均大於12.1 dB，低通埠反射損耗於DC-10.7GHz均大於16.4 dB，共同埠反射損耗於DC-18.2 GHz均大於12 dB。電路之平面面積約為10.5×24.9 mm2( )，整體外部體積大小為25.1×20.58×16 mm3( )。最後，將電路的量測特性與參考文獻比較整理於表。
相較於既有的文獻，本論文提出懸置帶線架構準集總元件雙工器的高頻寄生效應萃取方法與修正電路架構，並納入設計流程。再針對實做與量測時須要的SMA至懸置帶線轉接器、外罩金屬組裝流程等適當配置。最後，納入製程變異判段容忍的誤差範圍，而達成將準集總元件雙工器的設計系統化的目的。

This study proposed an systematic design flow for quasi-lumped suspended stripline diplexer. According to modified circuit model with parasitic effect on high-pass and low-pass filter layout, the diplexer design are accomplished step by step. Practical consideration and fabrication variation are also take into design.

[1]G.L. Matthaei, L. Young and E.M.T. Jone, “Microwave Filters, Impedance-Matching Networks and Coupling Structures,” New York, McGraw Hill, 1964.
[2]E.G. Cristal and G.L. Matthaei, “A Technique for the Design of Multiplexers Having Continuous Channels,” IEEE Trans. PTGMTT-12, pp. 88-93, January 1964.
[3]J. S. Hong and M. J. Lancaster, “Microstrip Filters for RF/Microwave Applications,” John Wiley & Sons. Inc., 2001.
[4]W. Menzel and A. Balalem, “Quasi-Lumped Suspended Stripline Filters and Diplexers”, IEEE Trans. Microw. Theory Tech., vol 53, no. 10, pp. 3230-3237,Oct. 2005.
[5]R. Rehner., M. Sterns, D. Schneiderbanger, S. Martius and L. Schmidt, “A Quasi-Lumped Ultra-Broadband Continuous SSL-Diplexer from DC to 80 GHz”, in IEEE MTT-S Int. Microw. Symp. Dig., pp. 1037-1040, 2009.
[6]I. Ashiq and A.P.S. Khanna, “Ultra-broadband contiguous planar DC-35–65 GHz diplexer using softboard suspended stripline technology”, in IEEE MTT-S Int. Microw. Symp. Dig., pp. 1-4, 2013.
[7]I. Ashiq and A.P.S. Khanna, “A novel ultra-broadband DC-36-to-66-GHz hybrid diplexer using waveguide and SSL technology”, in 44th Eur. Microw. Conf., 2014, pp. 1111 - 1114.
[8]C.-H. Lai, G.-T. Zhou and T.-G. Ma,“On-chip miniaturized diplexer using jointed dual-mode right-/left-handed synthesized coplanar waveguides on GIPD process”, IEEE Microw. Wireless Compon. Lett.,vol.24,no.4, pp. 245-247, April 2014.
[9]S. Sakhnenko, D. Orlenko, B. Vorotnikov, O. Aleksieiev, P. Komakha, P. Heide and M. Vossiek, “Ultra-low-profile small-size LTCC front-end module (FEM) for WLAN applications based on a novel diplexer design approach”, in IEEE MTT-S Int. Microw. Symp. Dig., pp. 609-612, 2009.
[10]W. Xia, X. Shang and M. J. Lancaster, “All-resonator-based waveguide diplexer with cross-couplings”, IEEE Electronic Lett.,vol.50,no.25, pp. 1948-1950, December 2014.