跳到主要內容

簡易檢索 / 詳目顯示

研究生: 陳德帆
De-Fan Chen
論文名稱: 應用於選擇性諧波消除脈波寬度調變於多電平逆變器的深度神經網路之晶片設計與實現
Chip Design and Implementation of a Deep Neural Network Applied to Selective Harmonic Elimination Pulse Width Modulation for Multilevel Inverter
指導教授: 薛木添
口試委員:
學位類別: 碩士
Master
系所名稱: 資訊電機學院 - 電機工程學系
Department of Electrical Engineering
論文出版年: 2025
畢業學年度: 114
語文別: 中文
論文頁數: 94
中文關鍵詞: 選擇性諧波消除脈波寬度調變多電平逆變器深度神經網路
相關次數: 點閱:13下載:0
分享至:
查詢本校圖書館目錄 查詢臺灣博碩士論文知識加值系統 勘誤回報
  • 在現今電力電子與再生能源技術快速發展的時代,多電平逆變器(Multilevel
    Inverter, MLI)因其具備高輸出電壓品質、低諧波失真及低開關損耗等特性,已成為
    高功率電能轉換應用中不可或缺的關鍵技術。然而,選擇性諧波消除脈波寬度調變
    (Selective Harmonic Elimination Pulse Width Modulation, SHEPWM)控制策略涉及高度非
    線性的多重方程求解,使得即時運算與硬體實現面臨挑戰。
    本論文針對十一階級聯式H橋多電平逆變器(CascadedH-Bridge,CHB-MLI),提出
    一套結合改良型粒子群演算法(ModifiedParticleSwarmOptimization, MPSO)與深度神
    經網路(DeepNeuralNetwork,DNN)模型之SHEPWM控制方法。研究首先利用MPSO
    求得不同調變指數(ModulationIndex) 下的最優開關角度,作為DNN模型的訓練資料,
    以實現開關角度預測模型,並以VerilogHDL完成整體硬體架構設計。
    本文的研究過程以Python進行演算法驗證,後續完成以Cell-based為基礎的完整晶
    片設計流程,並透過FPGA進行系統驗證。模擬與實驗結果顯示,本方法能有效抑制
    低次諧波、提升輸出波形品質,並顯著降低濾波器尺寸與運算延遲,展現其於多電平
    逆變器即時控制應用中的可行性與優勢。


    In recent years, multilevel inverters (MLIs) have played a crucial role in modern power
    electronics and renewable energy systems due to their advantages of high output voltage qual
    ity, low harmonic distortion, and reduced switching losses. However, the Selective Harmonic
    Elimination Pulse Width Modulation (SHEPWM) technique involves solving highly nonlin
    ear transcendental equations, which poses significant challenges for real-time computation and
    hardware implementation.
    This thesis focuses on an eleven-level Cascaded H-Bridge Multilevel Inverter (CHB-MLI)
    and proposes a SHEPWM control method that combines the Modified Particle Swarm Opti
    mization (MPSO) algorithm with a Deep Neural Network (DNN). The MPSO algorithm is first
    employed to obtain optimal switching angles under different modulation indices, which are then
    used to train the DNNmodelforfast, non-iterative prediction of switching angles. The proposed
    DNN adopts the ReLU and piecewise linear approximation (PLAN) Sigmoid activation func
    tions, and the overall hardware architecture is implemented using Verilog HDL.
    Theproposedmethodisverified through algorithm validation in Python, followed by a com
    plete cell-based chip design flow and FPGA implementation. Simulation and experimental re
    sults demonstrate that the proposed approach effectively suppresses low-order harmonics, im
    proves output waveform quality, and significantly reduces filter size and computation latency,
    proving its feasibility and advantages in real-time multilevel inverter control applications.

    第一章緒論. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 1.1背景介紹. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 1.2研究動機. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 1.3論文貢獻. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 1.4論文架構. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 第二章多電平逆變器拓撲與各式脈波寬度調變技術介紹. . . . . . . . . . . . . . . 4 2.1多電平逆變器拓撲. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 2.1.1二極體箝位型逆變器(DiodeClampedMLI) . . . . . . . . . . . . . . 4 2.1.2電容箝位型逆變器(FlyingCapacitorMLI,FC-MLI) . . . . . . . . . 5 2.1.3級聯式H橋型逆變器(CascadedH-BridgeMLI,CHB-MLI) . . . . . 6 2.2各類脈波寬度調變技術. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 2.2.1正弦脈波寬度調變(SinusoidalPulseWidthModulation,SPWM). 10 2.2.2空間向量脈波寬度調變(SpaceVectorPulseWidthModulation, SVPWM) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 2.2.3層級化載波脈波寬度調變(Level-ShiftedPWM,LSPWM). . . . . 12 2.2.4選擇性諧波消除脈波寬度調變(SelectiveHarmonicElimination PWM,SHEPWM). . . . . . . . . . . . . . . . . . . . . . . . . . . 13 2.3級聯式H橋多電平逆變器之SHEPWM數學建模. . . . . . . . . . . . . . 14 2.3.1 SHEPWM的數學原理與模型. . . . . . . . . . . . . . . . . . . . . 14 2.3.2 11-levelCHB架構下的方程組. . . . . . . . . . . . . . . . . . . . . 16 2.3.3 SHEPWM方程組求解辦法. . . . . . . . . . . . . . . . . . . . . . . 17 第三章選擇諧波消除脈波寬度調變技術演算法介紹. . . . . . . . . . . . . . . . . 19 3.1粒子群最佳化(ParticleSwarmOptimization,PSO)演算法. . . . . . . . . 19 3.2改良型粒子群最佳化演算法(MPSO) . . . . . . . . . . . . . . . . . . . . . . 23 3.2.1粒子初始位置之改進. . . . . . . . . . . . . . . . . . . . . . . . . . 23 3.2.2慣性權重之改進. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 3.2.3學習因子c1與c2之改進. . . . . . . . . . . . . . . . . . . . . . . . 25 3.3目標函數設計(ObjectiveFunction). . . . . . . . . . . . . . . . . . . . . . 26 3.4多樣性分析(DiversityAnalysis). . . . . . . . . . . . . . . . . . . . . . . 26 3.4.1 MPSO模擬結果與DNN導入動機. . . . . . . . . . . . . . . . . . . 27 第四章深度神經網路架構. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 4.1深度神經網路架構介紹. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 4.1.1神經元(Neuron) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 4.1.2激勵函數(ActivationFunction) . . . . . . . . . . . . . . . . . . . . . 31 4.1.3隱藏層與輸出層適合之激勵函數. . . . . . . . . . . . . . . . . . . 38 4.2 DNN學習與訓練. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 4.2.1損失函數(LossFunction) . . . . . . . . . . . . . . . . . . . . . . . . 39 4.2.2梯度下降法(GradientDescent) . . . . . . . . . . . . . . . . . . . . . 40 4.2.3優化器(Optimizers) . . . . . . . . . . . . . . . . . . . . . . . . . . . 41 4.3 DNN超參數優化(HyperparameterOptimization) . . . . . . . . . . . . . . . 42 4.3.1人工挑選(ManualSelection) . . . . . . . . . . . . . . . . . . . . . . 42 4.3.2網格搜尋(GridSearch) . . . . . . . . . . . . . . . . . . . . . . . . . 42 4.3.3貝氏優化(BayesianOptimization) . . . . . . . . . . . . . . . . . . . 43 4.3.4 DNN訓練流程與參數設定. . . . . . . . . . . . . . . . . . . . . . . 44 第五章系統架構與模擬結果. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47 5.1神經網路訓練結果. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47 5.1.1 DNN推論結果. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47 5.1.2 THD曲線比較. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48 5.1.3 Simulink系統建模與驗證. . . . . . . . . . . . . . . . . . . . . . . . 49 5.1.4 SHEPWM與PD-LSPWM系統性能比較. . . . . . . . . . . . . . . 49 5.1.5總結. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54 第六章電路架構與晶片實現. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55 6.1硬體設計規格. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55 6.2電路設計流程. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56 6.3硬體電路介紹. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57 6.3.1激勵函數硬體架構. . . . . . . . . . . . . . . . . . . . . . . . . . . 58 6.3.2深度神經網路模組硬體架構. . . . . . . . . . . . . . . . . . . . . . 63 6.3.3 SHEPWM訊號產生模組硬體架構. . . . . . . . . . . . . . . . . . . 66 6.3.4記憶體配置. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69 6.4模擬驗證. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70 6.5晶片設計結果. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71 6.5.1佈局圖. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71 6.5.2晶片核心電路面積分布. . . . . . . . . . . . . . . . . . . . . . . . . 73 6.5.3面積及功耗分布. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74 6.5.4錯誤覆蓋率. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75 6.5.5 LVS驗證結果. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76 6.5.6 CHIP總結. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77 第七章結論與未來展望. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78 參考文獻. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79

    [1] J. Rodriguez, J.-S. Lai, and F. Z. Peng, “Multilevel inverters: a survey of topologies, con
    trols, and applications,” IEEE Transactions on industrial electronics, vol. 49, no. 4, pp.
    724–738, 2002.
    [2] Y.-S. Lai and F.-S. Shyu, “Topology for hybrid multilevel inverter,” IEE Proceedings
    Electric Power Applications, vol. 149, no. 6, pp. 449–458, 2002.
    [3] I.Colak, E.Kabalci, andR.Bayindir, “Reviewofmultilevelvoltagesourceinvertertopolo
    gies and control schemes,” Energy conversion and management, vol. 52, no. 2, pp. 1114
    1128, 2011.
    [4] S. Debnath, J. Qin, B. Bahrani, M. Saeedifard, and P. Barbosa, “Operation, control, and
    applications of the modular multilevel converter: A review,” IEEE transactions on power
    electronics, vol. 30, no. 1, pp. 37–53, 2014.
    [5] M. S. Dahidah, G. Konstantinou, and V. G. Agelidis, “A review of multilevel selective
    harmonic elimination pwm: formulations, solving algorithms, implementation and appli
    cations,” IEEE Transactions on Power Electronics, vol. 30, no. 8, pp. 4091–4106, 2014.
    [6] W. Fei, X. Du, and B. Wu, “A generalized half-wave symmetry she-pwm formulation for
    multilevel voltage inverters,” IEEE Transactions on Industrial Electronics, vol. 57, no. 9,
    pp. 3030–3038, 2009.
    [7] J. Kennedy and R. Eberhart, “Particle swarm optimization,” in Proceedings of ICNN’95
    international conference on neural networks, vol. 4. ieee, 1995, pp. 1942–1948.
    [8] D. Tian and Z. Shi, “Mpso: Modified particle swarm optimization and its applications,”
    Swarm and evolutionary computation, vol. 41, pp. 49–68, 2018.
    [9] R. K. Ursem, “Diversity-guided evolutionary algorithms,” in International conference on
    parallel problem solving from nature. Springer, 2002, pp. 462–471.
    [10] M. Leshno, V. Y. Lin, A. Pinkus, and S. Schocken, “Multilayer feedforward networks
    withanonpolynomialactivationfunctioncanapproximateanyfunction,”Neuralnetworks,
    vol. 6, no. 6, pp. 861–867, 1993.
    [11] F. Agostinelli, M. Hoffman, P. Sadowski, and P. Baldi, “Learning activation functions to
    improve deep neural networks,” arXiv preprint arXiv:1412.6830, 2014.
    [12] S.-i. Amari, “Backpropagation and stochastic gradient descent method,” Neurocomputing,
    vol. 5, no. 4-5, pp. 185–196, 1993.
    [13] R. Hecht-Nielsen, “Theory of the backpropagation neural network,” in Neural networks
    for perception. Elsevier, 1992, pp. 65–93.
    [14] P. J. Werbos, “Backpropagation through time: what it does and how to do it,” Proceedings
    of the IEEE, vol. 78, no. 10, pp. 1550–1560, 2002.
    [15] D. E. Rumelhart, G. E. Hinton, and R. J. Williams, “Learning representations by back
    propagating errors,” nature, vol. 323, no. 6088, pp. 533–536, 1986.
    [16] T. Yu and H. Zhu, “Hyper-parameter optimization: A review of algorithms and applica
    tions,” arXiv preprint arXiv:2003.05689, 2020.
    [17] A. Tisan, S. Oniga, D. Mic, and A. Buchman, “Digital implementation of the sigmoid
    function for fpga circuits,” Acta Technica Napocensis Electronics and Telecommunica
    tions, vol. 50, no. 2, p. 6, 2009

    QR CODE
    :::