| 研究生: |
羅鋒 Feng Lo |
|---|---|
| 論文名稱: |
第二代高速數位用戶迴路中維特比解碼器之FPGA實現 FPGA Realization of the Viterbi Decoder for HDSL2 Systems |
| 指導教授: |
吳安宇
An-Yeu Wu |
| 口試委員: | |
| 學位類別: |
碩士 Master |
| 系所名稱: |
資訊電機學院 - 電機工程學系 Department of Electrical Engineering |
| 畢業學年度: | 88 |
| 語文別: | 中文 |
| 論文頁數: | 85 |
| 中文關鍵詞: | 第二代高速數位用戶迴路 、迴旋碼 、維等比解碼器 、維等比演算法 |
| 外文關鍵詞: | HDSL2, concolutional code, Viterbi Decoder, Viterbi Algorithm |
| 相關次數: | 點閱:14 下載:0 |
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第二代高速數位用戶迴路(HDSL2)被認為是使T1(1.544Mbps)服務更有經濟效率的解決方案。其最大的特點在於利用目前已架構的電話線用戶迴路即可提供T1服務,而且傳輸距離比既有的解決方案還遠。為達此目標,在HDSL2標準中,使用由脈衝振幅調變(PAM)及迴旋碼(convolutional code)所組成格子碼(TCM)為編碼標準。
在本論文中,我們實現了適用於HDSL2系統之迴旋碼編/解碼器。相較於編碼器,解碼器的電路複雜了許多,而且在實際硬體實現時,有許多要素需要列入考慮。在設計的過程中,我們針對實現維特比解碼器(Viterbi decoder)的要素加以探討,並且選定我們所要採用的架構;接著,我們以Matlab程式驗證整個編/解碼運作的過程,並以Verilog硬體描述語言來模擬及驗證電路的正確性。最後,我們以Altera FLEX 10K200E來實現我們的設計。
In this thesis, we focus on the realization of the convolutional encoder/decoder. The hardware complexity of the decoder is much complicated than the encoder, and there are several implementation issues. In realization, we discuss the implementation issues and a proposed architecture is presented at first. Then, the encoding/decoding process is simulated Matlab program and verified by Verilog HDL. Finally, the encoder/decoder is realized by the FPGA device.
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