跳到主要內容

簡易檢索 / 詳目顯示

研究生: 羅鋒
Feng Lo
論文名稱: 第二代高速數位用戶迴路中維特比解碼器之FPGA實現
FPGA Realization of the Viterbi Decoder for HDSL2 Systems
指導教授: 吳安宇
An-Yeu Wu
口試委員:
學位類別: 碩士
Master
系所名稱: 資訊電機學院 - 電機工程學系
Department of Electrical Engineering
畢業學年度: 88
語文別: 中文
論文頁數: 85
中文關鍵詞: 第二代高速數位用戶迴路迴旋碼維等比解碼器維等比演算法
外文關鍵詞: HDSL2, concolutional code, Viterbi Decoder, Viterbi Algorithm
相關次數: 點閱:14下載:0
分享至:
查詢本校圖書館目錄 查詢臺灣博碩士論文知識加值系統 勘誤回報
  • 第二代高速數位用戶迴路(HDSL2)被認為是使T1(1.544Mbps)服務更有經濟效率的解決方案。其最大的特點在於利用目前已架構的電話線用戶迴路即可提供T1服務,而且傳輸距離比既有的解決方案還遠。為達此目標,在HDSL2標準中,使用由脈衝振幅調變(PAM)及迴旋碼(convolutional code)所組成格子碼(TCM)為編碼標準。
    在本論文中,我們實現了適用於HDSL2系統之迴旋碼編/解碼器。相較於編碼器,解碼器的電路複雜了許多,而且在實際硬體實現時,有許多要素需要列入考慮。在設計的過程中,我們針對實現維特比解碼器(Viterbi decoder)的要素加以探討,並且選定我們所要採用的架構;接著,我們以Matlab程式驗證整個編/解碼運作的過程,並以Verilog硬體描述語言來模擬及驗證電路的正確性。最後,我們以Altera FLEX 10K200E來實現我們的設計。



    In this thesis, we focus on the realization of the convolutional encoder/decoder. The hardware complexity of the decoder is much complicated than the encoder, and there are several implementation issues. In realization, we discuss the implementation issues and a proposed architecture is presented at first. Then, the encoding/decoding process is simulated Matlab program and verified by Verilog HDL. Finally, the encoder/decoder is realized by the FPGA device.

    CHAPTER 1 INTRODUCTION1 1.1THE HDSL2 SYSTEM1 1.2MOTIVATION AND OBJECTIVE4 1.3THESIS ORGANIZATION6 CHAPTER 2 CONVOLUTIONAL CODES AND THE VITERBI ALGORITHM7 2.1CONVOLUTIONAL CODES8 2.2THE CONVOLUTIONAL ENCODER IN HDSL2 SYSTEMS14 2.3THE VITERBI ALGORITHM17 CHAPTER 3 IMPLEMENTATION ISSUES OF VITERBI DECODERS25 3.1METRICS NORMALIZATION SCHEMES25 3.2SURVIVOR MEMORY MANAGEMENT IN VITERBI DECODERS30 3.3ACSU SHARING42 3.4ARCHITECTURES FOR THE PROPOSED VITERBI DECODER46 CHAPTER 4 FPGA REALIZATION49 4.1INTRODUCTION TO FPGAS49 4.2ALTERA FLEX 10K200E51 4.3FPGA DESIGN FLOW54 4.4MATLAB SIMULATION RESULTS56 4.5REALIZATION60 CHAPTER 5 CONCLUSION71 5.1FUTURE WORKS71 REFERENCE73 APPENDIX75

    [1] Http://www.hdsl2.org
    [2] D. J. Rauschmayer, ADSL/VDSL Principles, Macmillan Technical Publishing, Indianapolis, 1999.
    [3] Draft for HDSL2 Standard, Letter Ballot, ANSI T1E1.4, June 1999.
    [4] E. Biglieri, D. Divsalar, P. J. Mclane and M. K. Simon, Introduction to trellis-coded modulation with applications, Maxwell Macmillan, Canada, 1991.
    [5] S. Lin and D. J. Costello, Jr., Error Control Coding, Prentice-Hall, New Jersey, 1982
    [6] R. E. Ziemer, R. L. Peterson, Introduction to Digital Communication, Macmillan, New York, 1992.
    [7] A. J. Viterbi, "Error Bounds for Convolutional Codes and an Asymptotically Optimum Decoding Algorithm," IEEE Trans. on Information Theory, Vol. IT-13, pp. 260-269, April 1967.
    [8] A. J. Viterbi, "Convolutional Codes and Their Performance in Communication Systems," IEEE Trans. on Communication Technology, Vol. COM-19, pp. 751-772, October 1971.
    [9] G. D. Forney, "The Viterbi Algorithm," Proceedings of the IEEE, Vol. 61, pp268-278, March 1973.
    [10] G. D. Forney, "Convolutional Codes II: Maximum Likelihood Decoding," Information and Control, Vol. 25, pp. 222-226, July 1974.
    [11] Andries P. Hekstra, "An alternative to metric rescaling in Viterbi decoders," IEEE Trans. on Commu., vol. COM-37, no. 11, pp. 1220-1222, Nov. 1989.
    [12] C. Shung, P. Siegel, G. Ungerbock, and H. Thapar, "VLSI Architectures for Metric Normalization in the Viterbi Algorithm," in Proceedings of the IEEE International Conference on Communications, pp. 1723-1728, IEEE, 1990.
    [13] Ivan M. Onyszchuk, "Truncation Length for Viterbi Decoding," IEEE trans. Commu., vol. COM-39, pp. 1023-1026, July 1991.
    [14] P. J. Black and T. H. Y. Meng, "Hybrid Survivor Path Architecture for Viterbi Decoders," in Proc. ICASSP 93, 1993, pp. I-433-I-436.
    [15] J. Sparso, H. J. Jorgensen, E. Paaske, S. Pedersen and T. R. Petersen, " An Area-Efficient Topology for VLSI Implementation of Viterbi Decoders and Other Shuffle-Exchange Type structures," IEEE Journal of Solid-State Circuits, vol. 26, no. 2, Feb. 1991.
    [16] M. Boo, F. Arguello, J. D. Bruguera, R. Doallo and E. L. Zapata, "High-Performance VLSI Architecture for the Viterbi Algorithm," IEEE Trans. Commu., Vol. 45, no. 2, Feb. 1997.
    [17] M. D Ciletti, Modeling, Synthesis, and Rapid Prototyping with the Verilog HDL, Prentice-Hall Inc., New Jersey, 1999
    [18] Altera Digital Library, Altera Inc., Jan. 2000

    QR CODE
    :::