使用矽穿孔（through silicon via）的三維整合技術是目前被大家公認的積體電路設計技術之一。為了克服記憶體不足，邏輯與動態隨機存取記憶體（DRAM）堆疊式三維整合晶片是一種有效的方法。由於邏輯與動態隨機存取記憶體可能來自不同的製造商，對一個堆疊式三維整合者有效的測試與診斷矽穿孔是很重要的。此外，堆疊過程可能最造成瑕疵(defect）散落。堆疊後的良率提升也是很需要的。
在本論文的第一部分，我們提出應用於邏輯與動態隨機存取記憶體（DRAM）堆疊式可程式化內建自我測試電路（built-in self-test )。內建自我測試電路產生控制訊號給動態隨機存取記憶體中的類1149.1邊界掃描（boundary scan），還有產生測試樣型（test pattern）去涵蓋（cover）邏輯與動態隨機存取記憶體間矽穿孔的永駐錯誤（stuck-at fault）與開路錯誤（open fault）。我們也提出一個診斷出永駐錯誤與開路錯誤位置的演算法。除此之外，自我測試電路可以產生測試樣品經由邏輯的邊界掃描給動態隨機存取記憶體。對於一個四通道512位元寬輸入輸出動態隨機存取記憶體（wide I/O DRAM），我們的測試和診斷演算法需要4754個時脈週期數。自我測試電路使用TSMC 90nm製程實現的面積為7359.4um2。
在本論文的第二部分，我們提出一個內建自我修復方法（BISR）來提升三維動態隨機存取記憶體，其中利用了通道間冗餘互相修復方法（inter-channel redundancy），此方法可以提升了冗餘利用率。我們也提出內建冗餘分析(BIRA)演算法來分配冗餘到通道間。模擬實驗可以看出在平均值為6時，我們提出的分法相較於傳統方法提升了20.3%的修復率（repair rate）。對一個32G位元的動態隨機存取記憶體，自我修復電路使用TSMC 90nm製程實現的面積為47880um2。

Three-dimensional (3D) integration technology using through-silicon via (TSV) has been acknowledged as one integrated circuit (IC) design technology. Logic and dynamic random access memory(DRAM) stacked 3D IC is considered as one effective approach for overcoming memory wall.
Since logic and DRAM dies may come from different sources, effective test and diagnosis method for TSVs are imperative for the 3D IC integrator. Furthermore, the stacking process may induce defects. Post-bond yield-enhancement techniques for DRAM stacks are needed.
In the first part of this thesis, we propose a programmable built-in self-test (BIST) scheme for logic and DRAM stacked 3D ICs. The BIST can generate control signals for the 1149.1-like bboundary scan in the DRAMdies and test patterns for covering the stuck-at and open faults of TSVs between the DRAM dies and the logic die. Also, a diagnosis test algorithm is proposed to locate the positions of stuck-at and open faults. Furthermore, the BIST can generate the test patterns for
DRAM dies through the boundary scan in the logic die. The test and diagnosis algorithm needs 4754 clock cycles to locate faults for a four channel 512-bit datawidth wide I/O DRAM. The area of the BIST is only 7359.4 um2 using TSMC 90nm CMOS standard cell library.
In the second part of this thesis, a post-bond built-in self-repair (BISR) scheme is proposed to enhance the yield of 3D DRAMs by using inter-channel redundancy. The inter-channel redundancy can increase the utilization of redundancies. Built-in redundancy analysis (BIRA) algorithms are also proposed to allocate the inter-die redundancy. Simulation results show that the proposed interchannel redundancy scheme can achieve 20.3% increment of repair rate at most than a typical
redundancy word architecture when the mean value is 6. The area of BISR is 47880 um2 using TSMC 90nm CMOS standard cell library for a 32G-bit DRAM.

[1] Provisional Report of the IEEE P1838 Defect tiger team, “3D-IC defect investigation.” July. 2012.
[2] S. Deutsch, B. Keller, V. Chickermane, S. Mukherjee, N. Sood, S. Goel, J. Chen, A. Mehta, F. Lee,
and E. Marinissen, “DfT architecture and ATPG for interconnect tests of JEDEC Wide-I/O memoryon-
logic die stacks,” in Proc. Int’l Test Conf. (ITC), Nov 2012, pp. 1–10.
[3] E. Marinissen, C.-C. Chi, J. Verbree, and M. Konijnenburg, “A DfT architecture for 3D-SICs based on
a standardizable die wrapper,” in Jour. of Electronic Testing: Theory and Applications, Feb 2012, pp.
73–92.
[4] M. Taouil, M. Masadeh, S. Hamdioui, and E. Marinissen, “Interconnect test for 3D stacked memoryon-
logic,” in Proc. Conf. Design, Automation, and Test in Europe (DATE), March 2014, pp. 1–6.
[5] E. Marinissen, C.-C. Chi, J. Verbree, and M. Konijnenburg, “3D DfT architecture for pre-bond and
post-bond testing,” in IEEE International 3D Systems Integration Conference (3DIC), Nov 2010, pp.
1–8.
[6] A. Ohba, S. Ohbayashi, T. Shiomi, S. Takano, K. Anami, H. Honda, Y. Ishigaki, M. Hatanaka, S. Nagao,
and S. Kayano, “A 7 ns 1 mb BiCMOS ECL sramwith shift redundancy,” IEEE Jour. of Solid-State
Circuits, vol. 26, no. 4, pp. 507–512, Apr 1991.
[7] V. Schober, S. Paul, and O. Picot, “Memory built-in self-repair using redundant words,” in Proc. Int’l
Test Conf. (ITC), 2001, pp. 995–1001.
[8] Y.-J. Huang and J.-F. Li, “Low-cost self-test techniques for small RAMs in SOCs using enhanced
IEEE 1500 test wrappers,” IEEE Transactions on Very Large Scale Integration (VLSI) Systems, vol. 20,
no. 11, pp. 2123–2127, Nov 2012.
[9] Y.-J. Huang, Y.-C. You, and J.-F. Li, “Enhanced IEEE 1500 test wrapper for testing small rams in
SOCs,” in IEEE International SOC Conference (SOCC), Sept 2010, pp. 236–240.
[10] Y. Xie, G. H. Loh, B. Black, and K. Bernstein, “Design space exploration for 3D architecture,” ACM
Journal on Emerging Technologies in Computing Systems, vol. 2, no. 2, pp. 65–103, Apr. 2006.
[11] J.-Q. Lu, “3-D hyperintegration and packaging technologies for micronano systems,” Proceedings of
the IEEE, vol. 97, no. 1, pp. 18–30, Jan. 2009.
[12] M. Motoyoshi, “Through-silicon via (TSV),” Proceedings of the IEEE, vol. 97, no. 1, pp. 43–48, Jan.
2009.
[13] JEDEC, “JEDEC wide I/O single data rate,” http://www.jedec.org/, Dec. 2011.
[14] ——, “JEDEC high bandwidth memory (HBM) DRAM,” Oct. 2013.
[15] Hybird memory cube consortium, “HMC specification 1.0,” Jan. 2013.
[16] A. Osseiran, “Test standards (with focus on IEEE1149.1),” in Proceedings of the 38th Midwest Symposium
on Circuits and Systems, vol. 2, Aug 1995, pp. 708–711 vol.2.
[17] “IEEE standard testability method for embedded core-based integrated circuits,” IEEE Std 1500-2005,
pp. 1–117, 2005.
[18] M. Cuviello, S. Dey, X. Bai, and Y. Zhao, “Fault modeling and simulation for crosstalk in systemon-
chip interconnects,” in IEEE Trans. on Computer-Aided Design of Integrated Circuits and Systems,
Nov 1999, pp. 297–303.
[19] A.-C. Hsieh and T. Hwang, “TSV redundancy: architecture and design issues in 3-D IC,” IEEE Trans.
on Reliability, vol. 20, no. 4, pp. 711–722, April 2012.
[20] J. Rajski and J. Tyszer, “Fault diagnosis of TSV-based interconnects in 3-D stacked designs,” in Proc.
Int’l Test Conf. (ITC), Sept 2013, pp. 1–9.
[21] C.-C. Chi, C.-W. Wu, M.-J. Wang, and H.-C. Lin, “3D-IC interconnect test, diagnosis, and repair,” in
Proc. IEEE VLSI Test Symp. (VTS), April 2013, pp. 1–6.
[22] Y.-J. Huang, J.-F. Li, J.-J. Chen, D.-M. Kwai, Y.-F. Chou, and C.-W. Wu, “A built-in self-test scheme
for the post-bond test of TSVs in 3D ICs,” in Proc. IEEE VLSI Test Symp. (VTS),May 2011, pp. 20–25.
[23] V. Pasca, L. Anghel, and M. Benabdenbi, “Configurable thru-silicon-via interconnect built-in self-test
and diagnosis,” in Latin American Test Workshop (LATW), March 2011, pp. 1–6.
[24] C.-W. Chou, Y.-J. Huang, and J.-F. Li, “A built-in self-repair scheme for 3-D RAMs with interdie
redundancy,” IEEE Trans. on Computer-Aided Design of Integrated Circuits and Systems, vol. 32,
no. 4, pp. 572–583, April 2013.
[25] ——, “Yield-enhancement techniques for 3D random access memories,” in International Symposium
on VLSI Design Automation and Test (VLSI-DAT), April 2010, pp. 104–107.
[26] L. Jiang, R. Ye, and Q. Xu, “Yield enhancement for 3d-stacked memory by redundancy sharing across
dies,” in Proc. IEEE/ACM Int’l Conf. on Computer-Aided Design (ICCAD), Nov 2010, pp. 230–234.
[27] B.-Y. Lin et al., “Redundancy aritectures for channel-based 3D DRAM yield improvement,” in Proc.
Int’l Test Conf. (ITC), 2014, pp. 1–7.
[28] D. Niggemeyer, M. Redeker, and J. Otterstedt, “Integration of non-classical faults in standard march
tests,” in Proc. IEEE Int’l Workshop on Memory Technology, Design and Testing (MTDT), Aug 1998,
pp. 91–96.
[29] E. Marinissen, J. Verbree, and M. Konijnenburg, “A structured and scalable test access architecture for
TSV-based 3D stacked ICs,” in Proc. IEEE VLSI Test Symp. (VTS), April 2010, pp. 269–274.
[30] Y.-J. Huang, J.-F. Li, and C.-W. Chou, “Post-bond test techniques for TSVs with crosstalk faults in 3D
ICs,” in Proc. Conf. Design, Automation, and Test in Europe (DATE), April 2012, pp. 1–4.
[31] P.Wanger., “Interconnect testing with boundary scan,” in Proc. Int’l Test Conf. (ITC), 1987, pp. 52–57.
[32] E. Marinissen, B. Vermeulen, H. Hollmann, and R. Bennetts, “Minimizing pattern count for interconnect
test under a ground bounce constraint,” IEEE Design & Test of Computers, vol. 20, no. 2, pp.
8–18, Mar 2003.
[33] T.-W. Tseng, J.-F. Li, and C.-C. Hsu, “ReBISR: a reconfigurable built-in self-repair scheme for random
access memories in SOCs,” IEEE Trans. on VLSI Systems, vol. 18, no. 6, pp. 921–932, June 2010.
[34] C.-C. Yang, J.-F. Li, Y.-C. Yu, K.-T. Wu, C.-Y. Lo, C.-H. Chen, J.-S. Lai, D.-M. Kwai, and Y.-F.
Chou, “A hybrid built-in self-test scheme for DRAMs,” in International Symposium on VLSI Design,
Automation and Test (VLSI-DAT), April 2015, pp. 1–4.
[35] R.-F. Huang, J.-F. Li, J.-C. Yeh, and C.-W. Wu, “A simulator for evaluating redundancy analysis algorithms
of repairable embedded memories,” in Proc. IEEE Int’l Workshop on Memory Technology,
Design and Testing (MTDT), 2002, pp. 68–73.
[36] C.-T. Huang, C.-F. Wu, J.-F. Li, and C.-W. Wu, “Built-in redundancy analysis for memory yield improvement,”
IEEE Trans. on Reliability, vol. 52, no. 4, pp. 386–399, Dec. 2003.
[37] L. Jiang, R. Ye, and Q. Xu, “Yield enhancement for 3D-stacked memory by redundancy sharing across
dies,” in Proc. IEEE/ACM Int’l Conf. on Computer-Aided Design (ICCAD), Nov 2010, pp. 230–234.
[38] M. Taouil and S. Hamdioui, “Layer redundancy based yield improvement for 3D wafer-to-wafer
stacked memories,” in IEEE European Test Symposium (ETS), May 2011, pp. 45–50.
[39] C.-C. Chi, Y.-F. Chou, D.-M. Kwai, Y.-Y. Hsiao, C.-W. Wu, Y.-T. Hsing, L.-M. Denq, and T.-H.
Lin, “3D-IC BISR for stacked memories using cross-die spares,” in International Symposium on VLSI
Design, Automation, and Test (VLSI-DAT), April 2012, pp. 1–4.
[40] X.Wang, D. Vasudevan, and H.-H. Lee, “Global built-in self-repair for 3D memories with redundancy
sharing and parallel testing,” in IEEE International 3D Systems Integration Conference (3DIC), Jan
2012, pp. 1–8.
[41] B. Lin, W. Chiang, C. Wu, M. Lee, H. Lin, C. Peng, and M. Wang, “Configurable cubical redundancy
schemes for channel-based 3D DRAMyield improvement,” Proc. Int’l Test Conf. (ITC), vol. PP, no. 99,
pp. 1–1, 2015.
[42] W. Kang, C. Lee, K. Cho, and S. Kang, “A die selection and matching method with two stages for yield
enhancement of 3-D memories,” in Test Symposium (ATS), 2013 22nd Asian, Nov 2013, pp. 301–306.