H.264快速橫向線型移動預估實現於Equator數位訊號處理器

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研究生：	徐意瑄 Yi-Shiuan Hsu
論文名稱：	H.264快速橫向線型移動預估實現於Equator數位訊號處理器 H.264 Fast Horizontal Line Search Motion Estimation Implemented on Equator DSP
指導教授：	張寶基 Pao-Chi Chang
口試委員:
學位類別：	碩士 Master
系所名稱：	資訊電機學院 - 通訊工程學系 Department of Communication Engineering
畢業學年度：	92
語文別：	中文
論文頁數：	97
中文關鍵詞：	可變區塊大小、移動預估演算法、H.264視訊編碼標準、多幅參考畫面、Equator DSP
外文關鍵詞：	Multi-Reference Frame, Variable Block Size, H.264 Video Coding, Motion Estimation, Equator DSP
相關次數：	點閱：8 下載：0
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H.264相較於以往的視訊標準，在壓縮效能上有很明顯的改進，然而所付出的代價即為造成編碼端複雜度的大量提升，以及增加硬體實現的困難度；而其計算的複雜度主要分布在可變區塊大小與多幅參考畫面機制下的移動預估計算。
為了讓H.264能達到即時應用的目標，本論文提出了快速橫向線型移動預估機制並實現於Equator DSP。快速橫向線型移動預估機制主要可分成兩部分－橫向線型搜尋演算法與整合可變區塊大小和多幅參考畫面的快速決策機制，橫向線型搜尋演算法利用Equator提供的128-bit暫存器架構來同時加速SAD計算與資料搬移。除此之外，我們在橫向線型搜尋演算法中也使用固定搜尋視窗來進一步降低SAD的計算量。在可變區塊大小演算法裡，我們提出了三階層的決策法則來省略不必要的移動預估計算量，另一方面我們也在多幅參考畫面演算法中使用快速中斷的決策方式來降低更多的計算量。由實驗結果可得知，我們於Equator上實現所提出的快速橫向線型移動預估機制，能使得執行移動預估計算量的時脈數大幅降低至98%，而不會造成視訊品質的大量失真。

H.264 video coding standard can achieve considerably higher coding efficiency than previous standards. However, this comes at a cost in considerably increased complexity at the encoder and thus increases the difficulty in hardware implementation. The computation complexity is mainly due to motion estimation in combination of variable block sizes and multi-reference frames.
To achieve the objective of real-time applications, we propose a fast multiple decision horizontal line search (MDHLS) scheme for H.264 and implement it on Equator DSP. The MDHLS mainly contains two parts, one is HLS algorithm and the other is a fast decision scheme for variable block sizes and multi-reference frames. HLS utilizes the 128-bit register of Equator to jointly accelerate SAD calculation and data access. And we employ a fixed search window size in HLS for further reducing SAD calculation. The proposed variable block size algorithm provides a three-stage decision rule to remove unnecessary computations of motion estimation. An early termination decision rule is also developed for multi-reference frame algorithm. Simulation results show MDHLS can achieve up to 98% cycle reduction in motion estimation implemented on Equator DSP and the coding efficiency is only slightly decreased.

目  錄
第一章 緒論	1
1.1簡介	1
1.2動機與目的	2
1.3論文架構	2
第二章 H.264與Equator DSP簡介	3
2.1視訊壓縮發展歷史	3
2.2 H.264整體壓縮效能改進情形	5
2.3 H.264視訊壓縮標準簡介	5
2.3.1 H.264架構介紹	6
2.3.2 Intra Prediction Mode	7
2.3.3 Inter Prediction Mode	10
2.3.4 Transform Coding	14
2.3.5 Universal VLC	18
2.4 H.264複雜度分析	19
2.5 Equator MAP-CA DSP簡介	21
2.5.1 Equator MAP-CA DSP架構概要	23
2.5.2指令集核心CPU	23
2.5.3暫存器	25
2.5.4可變長度編解碼(VLX) 	26
2.5.5影像濾波器(VF) 	27
2.5.6直接記憶體存取(DMA) 	28
2.5.7 C編譯器(C Compiler)	30
2.5.8 VLIW程式化	30
2.5.9適合移動預估演算法的硬體架構	32
第三章 H.264快速移動預估演算法簡介	34
3.1 H.264移動預估(Motion Estimation)壓縮流程	35
3.2 可變區塊大小(Variable Block Size)演算法	36
3.2.1 YCTB Algorithm	36
3.2.2 Tomoyuki''s Algorithm	38
3.2.3 FMBME Algorithm	40
3.3 多幅參考畫面(Multi-Frame)演算法	42
3.3.1 Huang''s Algorithm	42
3.3.2 FDVS Scheme	45
3.4 預測式線型移動預估(PLS)演算法	48
第四章 快速橫向線型移動預估演算法	51
4.1快速橫向線型移動預估演算法應用於H.264在Equator DSP上的分析	52
4.1.1 模式16x16快速橫向線型移動預估演算法	52
4.1.2 其他模式快速橫向線型移動預估演算法	55
4.1.3 快速橫向線型移動預估演算法效能分析比較	58
4.2 可變區塊大小演算法的改良 	62
4.2.1 Skip Mode決策	63
4.2.2 其它模式決策	65
4.3 多幅參考畫面演算法的改良	67
4.4 快速橫向線型移動預估(FHLS)演算法流程圖	69
第五章 實驗結果分析與討論	71
5.1 環境參數與所使用的視訊樣本	71
5.2 PSNR與Bitrate效能分析比較	74
5.3 加速效能分析比較	83
第六章 結論與未來展望	94
參考文獻	95
List of Figures
Figure 2.1視訊壓縮發展歷史流程圖	3
Figure 2.2 H.264，H.263，與MPEG-4壓縮效能之比較	5
Figure 2.3視訊壓縮標準H.264結構圖	7
Figure 2.4 4x4 luma prediction mode(1)	8
Figure 2.5 4x4 luma prediction mode(2)	9
Figure 2.6 16x16 luma prediction mode	10
Figure 2.7 Macroblock partition	11
Figure 2.8 Macroblock sub-partition	11
Figure 2.9樹狀結構分割圖	11
Figure 2.10殘餘量(Residual)的最佳分割模式	12
Figure 2.11 Inter coding參考向量方向示意圖	13
Figure 2.12 1-D Integer Transform and Inverse Transform	15
Figure 2.13 Luminance and Chrominance 編碼示意圖	16
Figure 2.14 Chrominace DC Transform	16
Figure 2.15 Simple Scan	16
Figure 2.16 Double Scan	16
Figure 2.17 H.264量化對照表	17
Figure 2.18 UVLC示意圖	18
Figure 2.19 H.264複雜度評估圖	20
Figure 2.20 Equator MAP-CA DSP硬體架構圖	22
Figure 2.21 Equator MAP-CA DSP暫存器示意圖	25
Figure 2.22 DMA與其他硬體關係示意圖	27
Figure 2.23 SAD加速之硬體架構示意圖	32
Figure 3.1 H.264最佳Inter Mode決策流程	35
Figure 3.2 四塊8x8區塊向量相關性示意圖	39
Figure 3.3 四塊8x8區塊向量不相關性示意圖	39
Figure 3.4 FMBME macroblock 切割四部份的示意圖	41
Figure 3.5 多幅參考畫面演算法比較	43
Figure 3.6 大小區塊移動向量差異示意圖	43
Figure 3.7 快速多幅參考畫面演算法流程圖	45
Figure 3.8 H.264多幅參考畫面演算法流程圖	45
Figure 3.9 Backward式移動向量合成圖	46
Figure 3.10 FDVS移動向量合成機制	46
Figure 3.11 FDVS應用於H.264流程圖	47
Figure 3.12 不同搜尋演算法記憶體存取比較圖	48
Figure 4.1 HLS在模式1下與FS比較的移動向量正確率(Akiyo)	54
Figure 4.2 HLS在模式1下與FS比較的移動向量正確率(Foreman)	54
Figure 4.3其他模式在不同方形視窗下與FS比較的移動向量正確率	55
Figure 4.4其它模式在不同長方形視窗下與FS比較的移動向量正確率	56
Figure 4.5 Proposed HLS 9X7長方形搜尋視窗圖	56
Figure 4.6 Proposed HLS 排程最佳化改善前後差異圖	57
Figure 4.7 Proposed HLS 與PLS相對於FS的PSNR比較圖	59
Figure 4.8 Proposed HLS相對於PLS的PSNR比較圖	59
Figure 4.9 Proposed HLS 與PLS相對於FS的bitrate比較圖	59
Figure 4.10 Proposed HLS相對於PLS的bitrate比較圖	60
Figure 4.11 Proposed HLS 與PLS相對於FS的cycle比較圖	61
Figure 4.12 Proposed HLS相對於PLS的cycle比較圖	61
Figure 4.13 Proposed相對於YCTB機制skip mode決策正確率比較圖	64
Figure 4.14 Proposed相對於YCTB機制其它模式決策正確率比較圖	66
Figure 4.15 Proposed相對於YCTB機制多幅參考畫面決策正確率比較	68
Figure 4.16快速橫向線型移動預估演算法流程	70
Figure 5.1 Proposed MDHLS機制與YCTB機制在Akiyo Sequence PSNR的比較	75
Figure 5.2 Proposed MDHLS機制與YCTB機制在Akiyo Sequence Bitrate的比較	75
Figure 5.3 Proposed MDHLS機制與YCTB機制在Bream Sequence PSNR的比較	76
Figure 5.4 Proposed MDHLS機制與YCTB機制在Bream Sequence Bitrate的比較	76
Figure 5.5 Proposed MDHLS機制與YCTB機制在Coastgaurd Sequence PSNR的比較	77
Figure 5.6 Proposed MDHLS機制與YCTB機制在Coastgaurd Sequence Bitrate的比較 77
Figure 5.7 Proposed MDHLS機制與YCTB機制在Foreman Sequence PSNR的比較	78
Figure 5.8 Proposed MDHLS機制與YCTB機制在Foreman Sequence Bitrate的比較	78
Figure 5.9 Proposed MDHLS機制與YCTB機制在News Sequence PSNR的比較	79
Figure 5.10 Proposed MDHLS機制與YCTB機制在News Sequence Bitrate的比較	79
Figure 5.11 Proposed MDHLS機制與YCTB機制在Stefan Sequence PSNR的比較	80
Figure 5.12 Proposed MDHLS機制與YCTB機制在Stefan Sequence Bitrate的比較	80
Figure 5.13 Proposed MDHLS機制與YCTB機制在Akiyo Sequence Speed的比較	84
Figure 5.14 Proposed MDHLS機制與YCTB機制在Bream Sequence Speed的比較	84
Figure 5.15 Proposed MDHLS機制與YCTB機制在Coastgaurd Sequence Speed的比較	85
Figure 5.16 Proposed MDHLS機制與YCTB機制在Foreman Sequence Speed的比較	85
Figure 5.17 Proposed MDHLS機制與YCTB機制在News Sequence Speed的比較	86
Figure 5.18 Proposed MDHLS機制與YCTB機制在Stefan Sequence Speed的比較	86
Figure 5.19 Proposed MDHLS機制與YCTB機制在Akiyo Sequence 加速比例的比較	88
Figure 5.20 Proposed MDHLS機制與YCTB機制在Bream Sequence 加速比例的比較	88
Figure 5.21 Proposed MDHLS機制與YCTB機制在Coastgaurd Sequence 加速比例的比較 89
Figure 5.22 Proposed MDHLS機制與YCTB機制在Foreman Sequence 加速比例的比較	89
Figure 5.23 Proposed MDHLS機制與YCTB機制在News Sequence 加速比例的比較	90
Figure 5.24 Proposed MDHLS機制與YCTB機制在Stefan Sequence 加速比例的比較	90
List of Tables
Table5.1視訊樣本的分類表	71
Table5.2 Proposed MDHLS機制與YCTB機制相對於FS在PSNR的統計比較 (單位: dB) 	81
Table5.3 Proposed MDHLS機制與YCTB機制相對於FS在Bitrate的統計比較 	81
Table5.4 Proposed MDHLS機制與YCTB機制在速度上的統計比較 (單位: Cycle Ratoio =實際執行cycles數 / 300 million cycles數)	87
Table5.5 Proposed MDHLS機制與FS在PC速度上的統計比較 (單位: frames / sec) 	93

                                

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