摘要
在本論文的主要目標是設計一個操作在3.3V之下、8位元、每秒150百萬次取樣(8bit,150Ms/s)的類比數位轉換器，以應用於RGB顯示器(LCD、CRT)及可攜式的儀表上。此類比數位轉換器採用平行管線化(Parallel- and-Pipelined)架構使硬體速度的需求度降低，同時可增加高速運算放大器的系統穩定時間(settling time)。此外，利用雙重取樣電路(double sampling)架構的取樣並保持電路相較傳統電路上在單位時間內有兩倍的取樣(sample)輸出。而在電路精確度的考量方面，而藉由重合一個位元的數位校正技術使得每一級(stage)的誤差容忍度有125毫伏(mV)；其中的電路之偏移誤差及所需比較器前級放大增益可藉由蒙地卡羅模擬以進行參數值估算。雙重取樣電路(double sampling)的原型晶片透過TSMC以0.25微米製程製作，面積約1.176mm×0.986mm，其量測結果與設計規格相符。而類比數位轉換器原型晶片透過TSMC以0.25微米製程製作，面積約3.136mm×2.534mm，功率消耗約467mW。

The subject of the thesis is to design an 8-bit, 150MS/s analog to digital converter(ADC) under a 3.3V supply. It can be applied in Gigabit Ethernet and RGB-to-LCD video signal processing interface circuits. This converter utilizes parallel-pipelined architecture to relax the hardware speed requirement. In addition, the Opamp can have a longer settling time under the same sampling rate. By means of double sample technique, the front end sample and hold (S/H) circuit has two times sampled data compared to traditional architectures. The coarse quantizer can tolerate 125mV comparator offset without overflow by digital error correction technique . The effect of process variation in the circuit will be estimated by Monte-Carlo simulation. The sample and hold circuit has been fabricated in TSMC 0.25μm CMOS process and occupies a chip area of 1.176mm*0.986mm. The measurement result meets our targeted specifications. The simulation result of the analog to digital converter has 0.5LSB INL and 0.6LSB DNL. The whole ADC chip is fabricated in TSMC 0.25μm CMOS process and the die size is 3.136mm*2.534mm.

參考文獻
[1] D.A. Johns amd K.Martin, Analog Integrated Circuit Design. John
Wiley and Sons,Inc.,1997.
[2] ”Principles of Data Conversion system Design” Behzad Razavi
[3]黃啟輝 碩士論文”125MHz 10位元之CMOS全差動取樣並保持電
路”1999年六月
[4] G.C.Temes, Y. Huang,and P.F. Ferguson,”A High-Frequency Track-and-Hold Stage with Offset and Gain Compensation,”IEEE Transactions on Circuits and Systems,vol.42,pp.559-561,AUGUST 1995
[5] G.C.Temes, Y. Huang,and P.F. Ferguson,”Novel High-Frequncy
Track-and-Hold Stages with offset and Gain Compensation
”pp.166-169,1996.
[6] “Design of Sample-and-Hold Amplifiers for High-Speed
Low-Voltage A/D Converters ” Behzad Razavi IEEE Custom Integrated
Circuit Conf. 1997
[7] L.Sumanen, M. Waltari, and K.Halonen, “A 10-bit 200MS/s CMOS
parallel pipeline A/D converter,”IEEE J.Solid-State Circuits, vol.36,
no.2.,pp.1048-1055, July 2001.
[8] Y.I. Park, S. Karthikenyan, F. Tsay , and E. Bartolome,
“A 10b 100Msample/s CMOS pipelined ADC with 1.8V power supply,”
in ISSCC Digest of Technical Papers, Feb 2001, pp.257-260
[9] Yun-Ti Wang, A 8-bit 150-MHz CMOS A/D Converter,
, PhD Thesis, University of California, Los Angeles,1999
[10] G.M.Yin, F.Op’t Eynde, and W. Sansen “A High-Speed CMOS
Comparator with 8-b resolution” IEEE J.Solid-State Circuits, vol.27,
no.2.,pp.208-211, DEC 1992.
[11] Behazad Razavi, Bruce Wooley, ”Design Technique for High
Speed High-Resolution Comparators”, IEEE J.Solid-State Circuits,
pp.1916-1926, Dec 1992.
[12] Jieh-Trorng Wu, Bruce Wooley, ” A 100-MHz Pipelined CMOS
Comparators”, IEEE J.Solid-State Circuits, vol. 23, no. 6, pp. 1379-1385,
Dec 1988.
[13] S.H. Lewis, H. S. Fetterman, G. F. Gross Jr.R. Ramachandran, and
others, ”A 10-b 20-Msamples/s analog-to-digital converter,” IEEE
J .Solid-State Circuits,vol. 27, no. 3, pp. 351-358, March 1992.
[14] K.Y. Kim, N. Kusayanagi and A.A. Abidi, “A 10-bit 100MS/s
CMOS A/D converter, “ in Proc. IEEE Custom Integrated Circuit
Conf.,May 1996,pp.419-422.
[15] Paul C. Yu, Hae-Seung Lee “A 2.5-V,12-b, 5-Msample/s Pipelined
CMOS ADC ” IEEE J.Solid-State Circuits, vol.31, no.12.,pp.1854-1861,
DEC 1996.
[16] P.C. Yu and H.-S. Lee, “A High-Swing 2-V CMOS Operational
Amplifier with Replica-Amp Gain Enhancement,” IEEE J.Solid-State
Circuits, vol.28,pp.1265-1272, Dec 1993.
[17] T.Cho, Low-power Low-voltage Analog-to-digital Conversion Techniques Using Pipelined Architectures, PhD Thesis, University of California, Berkely,1995
[18] Andrew Masami Abo, Design for Reliability of Low-voltage,
Switched-capacitor Circuits, PhD Thesis, University of California,
Berkely,1999
[19]Dan Kelly, Will Yang, Iuri Mehr, Mark Sayuk, Larry Singer ”A 3V
14b 75Msample/s CMOS ADC with 85dB SFDR at Nyquist” IEEE
ISSCC Digest of Technical Papers, Feb 2001
[20] Michael Choi, Asad A. Abidi ”A 6b 1.3Gsample/s A/D Converter in
0.35μm CMOS “IEEE Solid-state Circuit Conf. 2001.
[21]Li Lin, Design Technique for Parallel Pipelined ADC, MS. Thesis,
University of California, Berkely.