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研究生： 洪澤倫
Tze-Lun Hong
論文名稱： 時變通道下的OFDM傳輸系統設計:
Design of OFDM Transceiver for WLAN in the Time-Varying Channel:besed on IEEE 802.11a
指導教授： 張大中
Dah-Chung Chang
口試委員:
學位類別： 碩士
Master
系所名稱： 資訊電機學院 - 通訊工程學系
Department of Communication Engineering
畢業學年度： 94
語文別： 中文
論文頁數： 95
中文關鍵詞： 正交分頻多工 、時變通道 、通道估測
外文關鍵詞： channel estimation, OFDM, time-varying channel
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    • 此篇論文針對IEEE 802.11a收發機間的多種問題進行模擬，包括更正傳送機有能量損耗時的自動增益控制、更正收發機取樣頻率不同步的取樣時序回復模組、更正載波頻率不同步之載波頻率偏移更正模組、並針對多路徑通道與時變通道中的通道估計模組探討，並以VHDL語言設計基頻收發機系統，最後下載至FPGA發展板上，以訊號產生器與邏輯分析儀進行實作驗證。

    Some practical problems for an OFDM transceiver applied to WLAN are studied in this thesis, which include automatic gain control, sample timing offset, carrier frequency offset, and channel tracking in the time-varying channel. The IEEE 802.11a system is simulated and then a baseband prototype is designed with VHDL. Finally, the hardware implementation is verified on Xilinx FPGAs.

    第一章 序論……………………………………………………………01 1.1 前言………………………………………………………………01 1.2 研究動機…………………………………………………………01 1.3 內容大綱…………………………………………………………02 第二章 正交分頻多工系統與802.11a規格介紹 ……………………03 2.1正交分頻多工系統簡介 …………………………………………03 2.2 802.11a規格 ……………………………………………………06 2.3 收發機間之非理想特性與通道模型簡介………………………09 2.3.1 多路徑通道模型…………………………………………10 2.3.2 Jake’s Model時變通道模型 …………………………11 第三章 802.11a接收機演算法模擬 …………………………………13 3.0 接收機架構簡介…………………………………………13 3.1 自動增益控制系統………………………………………14 3.2 取樣頻率偏差與更正……………………………………19 3.3 封包偵測…………………………………………………25 3.4 符元同步…………………………………………………26 3.5 載波頻率偏移與更正……………………………………28 3.6 通道估測…………………………………………………34 3.6.1 利用長序列進行通道估測………………………34 3.6.2 通道追蹤…………………………………………36 3.6.3 通道追蹤開關……………………………………37 對於多路徑通道…………………………………37 對於時變通道……………………………………45 第四章 硬體電路模擬…………………………………………………56 4.0 VHDL寫作…………………………………………………56 4.1 802.11a傳送機硬體電路架構 …………………………57 4.2 802.11a接收機硬體電路架構 …………………………62 4.2.1 封包偵測模組硬體電路架構……………………65 4.2.2 符元同步模組硬體電路架構……………………68 4.2.3 載波頻率偏移補償模組硬體電路架構…………69 4.2.4 快速傅立葉轉換(FFT)模組硬體電路架構 ……71 4.2.5 通道估測與等化模組硬體電路架構……………74 4.2.6 接收機硬體電路實現之結果與比較……………75 第五章 FPGA實作………………………………………………………82 5.0 模擬環境與測試平台……………………………………82 5.1 硬體電路合成與資源使用量……………………………83 5.1.1 傳送機硬體電路合成圖與資源使用量…………83 5.1.2 接收機硬體電路合成圖與資源使用量…………85 5.2 實作驗證…………………………………………………91 第六章 結論與未來展望………………………………………………94 參考文獻 ………………………………………………………………95

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