| 研究生: |
林士哲 Shr-Je Lin |
|---|---|
| 論文名稱: |
利用元件庫資訊估測閘級階層設計的電流波形之研究 On Current Waveform Estimation of Gate Level Designs Using Cell Library Information |
| 指導教授: |
劉建男
Chien-Nan Liu |
| 口試委員: | |
| 學位類別: |
碩士 Master |
| 系所名稱: |
資訊電機學院 - 電機工程學系 Department of Electrical Engineering |
| 畢業學年度: | 93 |
| 語文別: | 中文 |
| 論文頁數: | 60 |
| 中文關鍵詞: | 閘級階層 、元件庫資訊 、電流波形 |
| 外文關鍵詞: | gate level, cell library, current waveform |
| 相關次數: | 點閱:11 下載:0 |
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目前高階電流模型這個研究方向開始受到重視,因為一旦可以快速的估計出電流的大小及變化情況,應用在電路設計中,將可用來估算電路中雜訊的大小,像是IR-drop,或是SSN (simultaneous switch noise)效應;這些會影響電路的效能或功能的雜訊,都可藉由電流的估計,來估算雜訊的大小。另外,對於power line的大小及佈局等等,都有很大的幫助。
在現今SOC(system-on-chip)時代,隨著電路的複雜度增加,模擬所花費的時間也隨著增加,為了加快模擬速度,必須把模擬的階層往上提高,為了同時確保一定的精準度與速度,因此選擇操作在閘極階層(gate-level)來做模擬。本篇論文提出一個新的想法,利用一些簡單的MOS特性,並經由現有的元件庫資訊,經過簡單運算就能準確的估計出電流波形。
而此論文的最終目標,想把此想法應用到現今現有的一些模擬軟體,因為此方法所需的資料,皆可由元件庫的資訊中取得,只需要外掛一些搜尋與計算的程式即可,不必耗費相當冗長的時間來跑SPICE的模擬,就可快速的從閘級模擬中獲得雜訊資料,這將會是個非常簡單且實用的方法。
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