本篇論文主要研究寬頻且低損耗之CMOS傳輸線變壓器，一共設計了三個傳輸線變壓器，包含兩個單端型式，其阻抗轉換比分別為1:9與1:4；與一個差動型式，其阻抗轉換比為1:4。在1:9傳輸線變壓器的設計中，使用寬邊耦合與多層金屬重疊的傳輸線來達到寬頻阻抗轉換的特性。從頻率4.4到6.6 GHz共2.2 GHz的頻寬中，其阻抗可從5.0 ±0.1轉換到50 ohms，當頻率為5.8 GHz時，有最小介入損耗為1.07 dB，且有164%的3-dB頻寬。同樣地，使用相同的方法設計出寬頻且低損耗的1:4傳輸線變壓器，其阻抗可從12.2 ±0.1轉換到50 ohms，涵蓋頻率範圍從2.1到3.3 GHz，在頻率2.6 GHz時有最小介入損耗，其值為1.0 dB，且3-dB頻寬為180%。此外，為了證明此1:4傳輸線變壓器的可用性，設計出一全積體化CMOS E類功率放大器，當操作頻率為2.6 GHz且工作電壓為3.6 V時，其最大輸出功率為24.7 dBm，功率增進效率為33.2%，功率增益為13.2 dB。由於傳輸線變壓器本身的寬頻特性，使得此功率放大器在頻率2.4到3.5GHz的範圍內，其輸出功率可達24.6 ±0.2 dBm。有別於前者，第三個傳輸線變壓器是差動型式，其阻抗轉換比為1:4，同樣是透過寬邊耦合傳輸線來達到寬頻且低損耗的阻抗轉換，其阻抗可從22 ±2轉換到100 ohms，頻率涵蓋範圍從3到6 GHz，在頻率5.3 GHz有0.9 dB的最小介入損耗。此外，將此1:4差動傳輸線變壓器應用到全積體化差動CMOS功率放大器中以驗證其可用性，結果顯示此功率放大器在3.5到6.0 GHz具有26.2 ±0.3 dBm平坦的功率輸出。
此外，本篇論文也提出了穿透矽通孔的射頻等效電路模型，在模型當中考慮了集膚效應以及有損的基板效應且適用頻率可達20 GHz。此穿透矽通孔使用0.18-μm SiGe BiCMOS製程製造而成，其直徑與深度分別為50 μm與100 μm。此等效電路模型的建立是透過量測的結果與穿透矽通孔本身的物理結構萃取而得，利用與頻率無關的集總元件來完全地詮釋與頻率相關的穿透矽通孔特性。更進一步地利用全積體化功率放大器的設計來驗證穿透矽通孔射頻等效電路模型的正確性，由於穿透矽通孔本身具有較低寄生阻抗的關係，使得有使用穿透矽通孔的功率放大器具有較佳的特性，相較於沒使用穿透矽通孔的功率放大器改善了0.5 dB的功率增益以及增加了2%的功率增進效率。

This dissertation focuses on the research of broadband and low-loss transmission-line transformer in 0.18 μm CMOS process. Three transmission-line transformers are designed, including two single-ended types with the impedance transformation ratio of 1:9 and 1:4 and one differential type with 1:4 impedance transformation ratio. In the design of 1:9 transmission-line transformer, broadside-coupled and multiple-metal stacked transmission lines are utilized to achieve a broadband impedance transformation 5.0 ±0.1 to 50 ohms, which covers the bandwidth of 2.2 GHz from 4.4 to 6.6 GHz. The measured minimum insertion loss is 1.07 dB at 5.8 GHz with a 3-dB bandwidth of 164 %. Similarly, a broadband and low-loss 1:4 transmission-line transformer is designed by using broadside-coupled and multiple-metal stacked transmission lines. The broadband impedance transformation is from 12.2 ±0.1 to 50 ohms within a 1.2-GHz bandwidth from 2.1 to 3.3 GHz, and the minimum insertion loss is 1.0 dB at 2.6 GHz with a 3-dB bandwidth of 180%. Besides, a fully-integrated CMOS Class-E power amplifier (PA) is designed to demonstrate the capability of the proposed 1:4 transmission-line transformer. This CMOS Class-E PA exhibits a maximum output power of 24.7 dBm at 2.6 GHz, where the power-added efficiency is 33.2% and the power gain is 13.2 dB under 3.6-V supply voltage. According to the broadband impedance transformation of the proposed 1:4 transmission-line transformer, this CMOS Class-E PA achieves broadband and flat output power of 24.6 ±0.2 dBm from 2.4 to 3.5 GHz. The third one is a differential transmission-line transformer with 1:4 impedance transformation ratio. The method of broadside-coupled transmission lines is used to achieve broadband impedance transformation and low insertion loss. The broadband impedance transformation is from 22 ± 2 to 100 ohms within a 3-GHz bandwidth from 3 to 6 GHz. The minimum insertion loss is 0.9 dB at 5.3 GHz. Besides, a fully-integrated and broadband differential CMOS PA is designed to verify the capability of the proposed 1:4 differential transmission-line transformer. This PA achieves flat output-power levels of 26.2 ±0.3 dBm from 3.5 to 6 GHz.
In addition, an RF model of through-silicon via (TSV) considering both skin-depth and lossy substrate effects up to 20 GHz is proposed. The TSV is fabricated in 0.18-μm SiGe BiCMOS process with the dimensions of 50-μm diameter and 100-μm depth. The equivalent circuit model is extracted from the measured results and physical structure of a single TSV. The frequency-dependent characteristics of TSV can be completely modeled by frequency- independent lumped elements through parameter extraction. Furthermore, a fully-integrated SiGe PA with TSVs is designed to verify the accuracy of the RF model of TSV. Meanwhile, a PA without TSVs is fabricated to compare the performance of the PA with TSVs. Due to the low-parasitic impedance of TSVs, the PA with TSVs achieves better performance than that without TSVs, where the improvement are 0.5 dB in power gain and 2 % in power-added efficiency, respectively.

[1] I. Aoki, S. D. Kee, D. B. Rutledge, and A. Hajimiri, “Fully integrated CMOS power amplifier design using the distributed active-transformer architecture,” IEEE J. Solid-State Circuits, vol. 37, no. 3, pp. 371–383, Mar. 2002.
[2] S. Kim, K. Lee, J. Lee, B. Kim, S. D. Kee, I. Aoki, and D. B. Rutledge, “An optimized design of distributed active transformer,” IEEE Trans. Microw. Theory Tech., vol. 53, no. 1, pp. 380–388, Jan. 2007.
[3] U. R. Pfeiffer and D. Goren, “A 23-dBm 60-GHz distributed active transformer in a silicon process technology,” IEEE Trans. Microw. Theory Tech., vol. 55, no. 5, pp. 857–865, May 2007.
[4] I. Aoki, S. Kee, R. Magoon, R. Aparicio, F. Bohn, J. Zachan, G. Hatcher, D. McClymont, and A. Hajimiri, “A fully-integrated quad-band GSM/GPRS CMOS power amplifier,” IEEE J. Solid-State Circuits, vol. 43, no. 12, pp. 2747–2758, Dec. 2008.
[5] G. Liu, P. Haldi, T.-J. K. Liu, and A. M. Niknejad, “Fully integrated CMOS power amplifier with efficiency enhancement at power back-off,” IEEE J. Solid-State Circuits, vol. 43, no. 3, pp. 600–609, Mar. 2008.
[6] P. Haldi, D. Chowdhury, P. Reynaert, G. Liu, and A. M. Niknejad, “A 5.8 GHz 1 V linear power amplifier using a novel on-chip transformer power combiner in standard 90 nm CMOS,” IEEE J. Solid-State Circuits, vol. 43, no. 5, pp. 1054–1063, May. 2008.
[7] A. Vasylyev, P. Weger, and W. Simburger, “Ultra-broadband 20.5–31 GHz monolithically-integrated CMOS power amplifier,” Electronics Lett., vol. 41, no. 23, pp. 1281–1282, 10th Nov. 2006.
[8] Y. Kim, C. Park, H. Kim, and S. Hong, “CMOS RF power amplifier with reconfigurable transformer,” Electronics Lett., vol. 42, no. 7, pp. 405–407, 30th Mar. 2006.
[9] C. Park, Y. Kim, H. Kim, and S. Hong, “Fully integrated 1.9-GHz CMOS power amplifier for polar transmitter applications,” Microw. Opt. Technol. Lett., vol. 48, no. 10, pp. 2053–2056, Oct. 2007.
[10] C. Park, Y. Kim, H. Kim, and S. Hong, “A 1.9-GHz CMOS power amplifier using three-port asymmetric transmission line transformer for a polar transmitter,” IEEE Trans. Microw. Theory Tech., vol. 55, no. 2, pp. 230–238, Feb. 2007.
[11] C. Park, Y. Kim, H. Kim, and S. Hong, “A 1.9-GHz triple-mode Class-E power amplifier for a polar transmitter,” IEEE Microw. and Wireless Compon. Lett., vol. 17, no. 2, pp. 148–150, Feb. 2007.
[12] C. Park, D. H. Lee, J. Han, and S. Hong, “Tournament-shaped magnetically coupled power-combiner architecture for RF CMOS power amplifier,” IEEE Trans. Microw. Theory Tech., vol. 55, no. 10, pp. 2034–2042, Oct. 2007.
[13] C. Park, S.-H. Baek, B.-H. Ku, and S. Hong, “A 1.9-GHz CMOS power amplifier using an interdigitated transmission line transformer,” Microw. Opt. Technol. Lett., vol. 49, no. 12, pp. 3162–3166, Dec. 2007.
[14] C. Park, J. Han, H. Kim, and S. Hong, “A 1.8-GHz CMOS power amplifier using a dual-primary transformer with improved efficiency in the low power region,” IEEE Trans. Microw. Theory Tech., vol. 56, no. 4, pp. 782–792, Apr. 2008.
[15] K. H. An, O. Lee, H. Kim, D. H. Lee, J. Han, K. S. Yang, Y. Kim, J. J. Chang, W. Woo, C.-H. Lee, H. Kim, and J. Laskar, “Power-combining transformer techniques for fully-integrated CMOS power amplifiers,” IEEE J. Solid-State Circuits, vol. 43, no. 5, pp. 1064–1075, May. 2008.
[16] K. H. An, D. H. Lee, O. Lee, H. Kim, J. Han, W. Kim, C.-H. Lee, H. Kim, and J. Laskar, “A 2.4 GHz fully integrated linear cmos power amplifier with discrete power control,” IEEE Microw. and Wireless Compon. Lett., vol. 19, no. 7, pp. 479–481, July 2009.
[17] O. Lee, K. H. An, H. Kim, D. H. Lee, J. Han, K. S. Yang, C.-H. Lee, H. Kim, and J. Laskar, “Analysis and design of fully integrated high-power parallel-circuit Class-E CMOS power amplifiers” IEEE Trans. Circuits and Syst. I: Reg. Papers, vol. 57, no. 3, pp. 725–734, Mar. 2010.
[18] C. L. Ruthroff, “Some broadband transformer,” Proc. IRE, vol. 47, pp. 1337 – 1342, Aug. 1959.
[19] M. Engles, R. H, Jansen, W, Daumann, R. M. Bertenburg, and F. J. Tegude, “Design methodology, measurement and application of MMIC transmission line transformers,” in IEEE MTT-S Int. Microw. Symp. Dig., 16–20 May 1995, vol. 3, pp. 1635–1638.
[20] R. F. Sobrany and I. D. Robertson, “Ruthroff transmission line transformers using multilayer technology,” Proc. 33rd European Microwave Conf., Munich, Germany, Oct. 2003, Vol. 2, pp. 559–562.
[21] Inder J. Bahl, “Broadband and compact impedance transformers for microwave circuits,” IEEE Microw. Mag., vol. 7, no. 4, pp. 56–62, Aug. 2006.
[22] I. Aoki, S. D. Kee, D. B. Rutledge, and A. Hajimiri, “Distributed active transformer—A new power-combining and impedance-transformation technique,” IEEE Trans. Microw. Theory Tech., vol. 50, no. 1, pp. 316–331, Jan. 2002.
[23] H.-K. Chiou, H.-Y. Liao, C.-C. Chen, S.-M. Wang, and C.-C. Chen, “A 2.6-GHz fully integrated CMOS power amplifier using power-combining transformer,” Microw. Opt. Technol. Lett., vol. 52, no. 2, pp. 299–302, Feb. 2010.
[24] P. Reynaert and M. S. J. Steyaert, “A 2.45-GHz 0.13-μm CMOS PA With Parallel Amplification,” IEEE J. Solid-State Circuits, vol. 42, no. 3, pp. 551–562, Mar. 2007.
[25] A. Hajimiri, “Distributed Integrated Circuits: An Alternative Approach to High-Frequency Design,” IEEE Communications Mag., vol. 40, no. 2, pp. 168–173, Feb. 2002
[26] P. Haldi, G. Liu, and A. M. Niknejad, “CMOS Compatible Transformer Power Combiner,” Electronics Lett., vol. 42, no. 19, pp. 1091–1092, 14th Sept. 2006.
[27] D. H. Lee, D. Baek, H. Kim, and S. Hong, “An on-chip low-loss 1:9 transmission line transformer and its model,” Microw. Opt. Technol. Lett., vol. 48, no. 10, pp.1936–1940, Oct. 2006.
[28] P. L. D. Abrie, Design of RF and Microwave Amplifiers and Oscillators. Norwood, MA: Artech House, 2000, ch. 6.
[29] H.-K. Chiou and T.-Y. Yang, “Low-loss and broadband asymmetric broadside-coupled balun for mixer design in 0.18-μm CMOS technology,” IEEE Trans. Microw. Theory Tech., vol. 56, no. 4, pp. 835–848, Apr. 2008.
[30] H.-K. Chiou and H.-Y. Liao, “Broadband and low-loss 1:9 transmission-line transformer in 0.18-μm CMOS process,” IEEE Electron Devices Lett., vol. 31, no. 9, pp. 921–923, Sept. 2010.
[31] Y. Yoon, H. Kim, J. Cha, O. Lee, H.S. Kim, W. Kim, C.-H. Lee, and J. Laskar, “Fully-integrated concurrent dual-band CMOS power amplifier with switchless matching network,” Electronics Lett., vol. 47, no. 11, pp. 659–661, 26th May 2011.
[32] H. Solar, G. Bistué, J. Legarda, E. Fernández, and R. Berenguer, “Design model for fully integrated high-performance linear CMOS power amplifiers,” IET Microwaves, Antennas & Propagat, vol. 5, no. 7, pp. 795–803, July 2011.
[33] C. Lu, A.-V. H. Pham, M. Shaw, and C. Saint, “Linearization of CMOS broadband power amplifiers through combined multigated transistors and capacitance compensation,” IEEE Trans. Microw. Theory Tech., vol. 55, no. 11, pp. 2320–2328, Nov. 2007.
[34] P.-C. Huang, K.-Y. Lin, and H. Wang, “A 4–17 GHz Darlington cascode broadband medium power amplifier in 0.18-μm CMOS technology,” IEEE Microw. and Wireless Compon. Lett., vol. 20, no. 1, pp. 43–45, Jan. 2010.
[35] H. Wang, C. Sideris, and A. Hajimiri, “A CMOS broadband power amplifier with a transformer-based high-order output matching network,” IEEE J. Solid-State Circuits, vol. 45, no. 12, pp. 2709–2722, Dec. 2010.
[36] P.-C. Huang, Z.-M. Tsai, K.-Y. Lin, and H. Wang, “A high-efficiency, broadband CMOS power amplifier for cognitive radio applications,” IEEE Trans. Microw. Theory Tech., vol. 58, no. 12, pp. 3556–3565, Dec. 2010.
[37] B. Jin, C. Zhao, and B. Kim, “A compact broadband transformer-based linear CMOS power amplifier design,” Microw. Opt. Technol. Lett., vol. 53, no. 2, pp. 422–425, Feb. 2011.
[38] J. H. Wu, J. Scholvin, and J. A. del Alamo, “Through-wafer interconnect in silicon for RFICs,” IEEE Trans. Electron Devices, vol. 51, no. 11, pp. 1765–1771, Nov. 2004.
[39] L. L. W. Leung and K. J. Chen, “Microwave characterization and modeling of high aspect ratio through-wafer interconnect vias in silicon substrates,” IEEE Trans. Microw. Theory Tech., vol. 53, no. 8, pp. 2472–2480, Aug. 2005.
[40] L. Cadix, C. Bermond, C. Fuchs, A. Farcy, P. Leduc, L. DiCioccio, M. Assous, M. Rousseau, F. Lorut, L.L. Chapelon, B. Flechet, N. Sillon, and P. Ancey, “RF characterization and modelling of high density Through Silicon Vias for 3D chip stacking,” Microelectron. Eng., vol. 87, no. 3, pp. 491–495, Mar. 2010.
[41] Y. Cao, R. A. Groves, X. Huang, N. D. Zamdmer, J.-O. Plouchart, R. A. Wachnik, T.-J. King, and C. Hu, “Frequency-independent equivalent-circuit model for on-chip spiral inductors,” IEEE J. Solid-State Circuits, vol. 38, no. 3, pp. 419–426, Mar. 2003.
[42] S. Kim and D. P. Neikirk, “Compact equivalent circuit model for the skin effect,” in Proc. IEEE Microw. Theory and Tech. Symp. Dig., 1996, pp. 1815–1818.
[43] D. K. Cheng, Fundamentals of Engineering Electromagnetics, Englewood Chliffs, NJ: Prentice-Hall, 1993.
[44] Inder J. Bahl, Lumped Elements for RF and Microwave Circuits. Norwood, MA: Artech House, 2003, ch. 9.