從超大型積體電路設計一路演進到奈米時代，現今晶片設計的技術日趨複雜，連帶影響電源網路（Power/Ground Network）之尺寸大幅增加，單看供電網路上所連接的標準元件數量就已經超過百萬等級的數量，更不用說電源網路上的電阻、電容元件更是遠超過如此龐大的數量。

傳統的設計流程中，為了評估整體晶片準確的電壓、電流值，通常會在電路設計的後期階段，進行芯片封裝板的模擬（Chip-Package-Board Co-Simulation），在此階段要做到整體電源完整性的模擬需要耗費龐大的計算時間與硬體資源，若是能提供電源網路的化簡模型，便能夠大幅縮減每一次修改又模擬的時間，不僅能縮短晶片上市的時間，更能在日益縮短的產品週期中，增加重複測試的次數，加強產品的穩定性。

我們可以藉由模型降階（MOR）之技術產生化簡模型，這樣的技術過去已經發展多年，例如基於圖形的時間常數平衡化減方法（TICER），基於投影的PRIMA、稀疏隱含投影法（SIP）。在如此龐大的電源網路中，衍出而來的電壓降形成主要問題，由於電路本身稀疏的特性，本篇論文採用基於稀疏隱含投影法（SIP）演算法為基礎所實做的平台上，提出適用於電源網路的節點保留方法（Node Retention），藉此找出並保留主導整體電路的主要節點，在可接受的電壓降精準度範圍內保留最少的節點，得到盡可能小的化簡模型。由最後的實驗結果可發現，相較單純的稀疏隱含投影法（SIP）配合隨機選點保留，經由提出的方法正確的保留節點能大幅提升精確度高達138倍。

As the VLSI advances into the nanometer era, modern chip design technology becomes more complex. As a result, the size of power/ground network dramatically increases; besides, the number of components connected on power/ground network is beyond millions, not to mention the number of resistances and capacitances in the power/ground network.

In the traditional design flow, in order to verify the accuracy of voltage and current in chip, the chip-package-board co-simulation is generally performed in late design stages. However, the co-simulation will cost a lot of time and computational resources. It’s necessary for us to develop a reduced core model of power/ground network to decrease the simulation time. The proposed model can not only shorten time-to-market but also strengthen the robustness of products.

We can develop the reduced core model by model-order-reduction (MOR) techniques. There are already many approaches such as graph-based methods TICER and projection-based methods PRIM and SIP. IR-drop is a major issue in such a large power/ground network causing power integrity problems. Due to the sparse characteristics of circuit, we implement the platform based on SIP in the thesis. The proposed node retention methods reserve dominant nodes in power/ground network and get reduced model as small as possible with acceptable accuracy. The experimental results shows that the proposed node retention methods can enhance accuracy up to 138 times compared to SIP with random node retention.

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