在PHOBOS的實驗中，利用相對重離子碰撞加速器（Relativistic Heavy-Ion Collider accelerator），藉著金原子和金原子的對撞，模擬這個最原始的狀態—夸克—膠子電漿態（Quark-Gluon Plasma）。為了能夠偵測到夸克—膠子電漿態（Quark-Gluon Plasma）的存在證據，PHOBOS實驗就以矽偵測器作為主要的偵測器。隨著實驗要求的不同，矽偵測器的幾何形狀也就有不同的設計，在PHOBOS的實驗中，所用的主要偵測器就是矽微條偵測器（Silicon Strip Detector，SSD）以及矽塊狀偵測器（Silicon Pad Detector，SPD）。而在本篇論文中，主要就是探討PHOBOS所用的SSD以及SPD的寄生電容（parasitic capacitance）的性質。
矽偵測器（SSD,SPD）的內部，寄生電容（parasitic capacitance）一直是受人討論的問題。因為它關係到這個偵測器的訊號和噪音的比例（signal-noise ratio），而且它很難從偵測器上直接地量測出來。為了能夠得到這些寄生電容的值，藉著K&S Model 4123點銲機讓欲測量P+塊狀區域的附近每個P+塊狀區域的偏壓電阻接地（bonding pad ground）。接著再用KEITHLEY Model 230電壓供應器以及KEITHLEY Model 590 CV Analyzer電容量測器，藉著Labview的整合，透過GPIB介面，控制電壓的輸出以及電容值的讀取。
經由一系列不同『接地』方式量測某一個單一P+塊狀區域的結果。結果得知，以訊號線（signal line）和第一層金屬（Metal_1）之間的電容和訊號線（signal line）和訊號線（signal line）之間的電容是構成寄生電容最主要的二個部分。為了能夠減少這二個部分的寄生電容，偵測器內部訊號線的設計以及Metal_1和Metal_2之間的絕緣層種類及厚度是必須要考慮的。

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