本篇論文中，主要是利用泰勒級數法開發一個四面體網格模組，並且用來模擬元件的特性，而為了能夠使模組可以以任意四面體當基本網格，我們選擇以重心來開發模組。根據我們的分析，在與其他方法進行比較後，我們發現泰勒級數法能夠完美的克服以往所遇見的問題，故我們選擇泰勒級數法來求得方程式裡所需要的四面體內部電場向量，完成程式模組後，設定四面體座標與電位，並且驗證此四面體的電場、電子流與電洞流，再來，將五顆四面體組合成一個單顆立方體電阻，比較其模擬值與計算出的理論值，以確認模組開發的精確性。最後，嘗試以兩種不同方法串接多顆立方體電阻時所發現的誤差，並探討其原因。

In this thesis, we develop a tetrahedron element module by using the Taylor series and use it to simulate 3D semiconductor device. In order to enable this module to be applied to arbitrary tetrahedron, we choose barycenter method to develop the module. According to our analysis, after comparing with other methods, we find that the Taylor series can overcome the problem in the past, so we choose the Taylor series to find the internal electric field vector. After completing the module, set the coordinates and potentials of the tetrahedron, and verify the electric field, the electron current density, and the hole current density. Then, the five tetrahedrons are combined into a cube resistor, and compare the simulated value with the theoretical value to confirm the accuracy of the module development. Finally, try to find the error when connecting multiple cube resistors in two different ways and discuss the reason.

[1]Y. M. Li, “Research on Development of Computer Simulation Methods for Semiconductor Devices and Nanostructures.” D. S. Thesis, Institute of Electronics, National Chiao Tung University, Taiwan, Republic of China, 2000.
[2]C. C Chang, C. H. Huang, J. F. Dai, S. J. Li, and Y. T. Tsai, “3-D Numerical Device Simulation Including Equivalent-Circuit Model”, IEDMS, 2002.
[3]G. W. Tang, “Generation of Tetrahedral/Prismatic Meshes and Its Applications in Microchannel Flows”, D. S, Thesis, Institute of AA, National Cheng Kung University, Taiwan, Republic of China, 2006.
[4]D. A Neamen, Semiconductor physics and devices, 3rd ed. McGraw-Hill Companies Inc., New York, 2003.
[5]R. E. Bank, D. J. Rose, and W. Fichtner, “Numerical methods for semiconductor device”, IEEE Trans, Electron Devices, vol. 30, no. 9, Sep. 1983.
[6]Y. Q. Hong, “Development of tetrahedron circumcenter element and its applications to 3D semiconductor device simulation” M. S. Thesis, Institute of EE, Nation Central University, Taiwan, Republic of China, 2017.
[7]J. H. Seo, Y. J. Yoon, S. Lee, J. H. Lee, S. Cho, and I. M. Kang, “Design and Analysis of Si-Based Arch-Shaped Gate-All-around (Gaa) Tunneling Field-Effect Transistor (T fet)”, Current Applied Physics, Vol. 15, pp. 208-212, 2015.
[8]D. G. Shih, “Finding internal vector from the plane equation and axis method in tetrahedron element for 3D semiconductor Device Simulation” M. S. Thesis, Institute of EE, Nation Central University, Taiwan, Republic of China, 2018.
[9]M. J. Zeng, “Development of Triangular element and its applications to arbitrary 2D semiconductor device” M. S. Thesis, Institute of EE, Nation Central University, Taiwan, Republic of China, 2014.
[10]B. Adolph and F. Bechstedt, “Ab initio second-harmonic susceptibilities of semiconductors : Generalized tetrahedron method and quasiparticle effects”, Physical Review B, 1998.
[11]K. Y. Hung, “Integration of Band Solver and BILU Solver for 3-D Device Simulation” M. S. Thesis, Institute of EE, Nation Central University, Taiwan, Republic of China, 2012.
[12]D. M. Wood, Alex Zunger, and R. De Groot. “Electronic structure of filled tetrahedral semiconductors.” Physical Review B 31.4 1985.
[13]J. S. Zhao, F. L. Chu and Z. J. Feng, “Kinematics of Spatial Parallel Manipulators with Tetrahedron Coordinates”, IEEE Trans, Robotics, vol. 30, no. 1, pp. 233-243, Feb. 2014.
[14]H. C. Casey, Devices for integrated circuits : silicon and III-V compound semiconductors. New York: John Wiley, 1999.
[15]M. Putti and C. Cordes, “Finite Element Approximation of The Diffusion Operator on Tetrahedral”, Society for Industrial and Applied Mathematics vol. 19, no. 4, pp. 1154-1168, 1998.
[16]W. H. Chiu, “Finding internal vector from the edge vector in arbitrary tetrahedron element for 3D semiconductor Device Simulation”, M. S. Thesis, Institute of EE, Nation Central University, Taiwan, Republic of China, pp. 29-31, 2017.
[17]M. C, Huang, “Area-Partition Problems in 2-D Semiconductor Device Simulation.” M. S. Thesis, Institute of EE, Nation Central University, Taiwan, Republic of China, 2015.
[18]L. T, Wang, “Development of point-added cube element and its application to Semiconductor Device Simulation”, M. S. Thesis, Institute of EE, Nation Central University, Taiwan, Republic of China, 2018.