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研究生： 林宇蓁
Yu-Chen Lin
論文名稱： 以RFSoC平台設計與實現DVB-S2多重符碼率收發機
Design and Implementation of DVB-S2 Multi-Symbol Rate Transceiver with RFSoC Platform
指導教授： 陳逸民
Yih-Min Chen
口試委員:
學位類別： 碩士
Master
系所名稱： 資訊電機學院 - 通訊工程學系
Department of Communication Engineering
論文出版年： 2025
畢業學年度： 113
語文別： 中文
論文頁數： 144
中文關鍵詞： 第二代數位衛星廣播 、多重符碼率 、升取 、降取 、多相濾波器 、費洛內插器 、數位訊號處理 、軟體定義無線電 、射頻系統晶片 、現場可程式化邏輯閘陣列
外文關鍵詞： DVB-S2, Multi-Symbol Rate, Up-Sampling, Down-Sampling, Polyphase Filter, Farrow Interpolator, Digital Signal Processing, Software Defined Radio, RFSoC, FPGA
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    • 隨著低軌道（Low Earth Orbit, LEO）衛星通訊技術的發展，第二代數位衛星廣播系統DVB-S2成為不可或缺的標準，此標準具有優秀的錯誤修正能力與高頻譜效率，整體系統於低訊雜比(Signal to Noise Ratio, SNR)的環境下仍能運作。
    本研究針對DVB-S2標準在衛星通訊中的應用，設計並實現支援多重符碼率(Multi-Symbol Rate)的收發機，旨在不調整系統取樣率的情況下，以數位訊號處裡的方式，使用多級的兩倍多相濾波器搭配小數倍率降取的費洛內插器(Farrow Interpolator)，實現可變的升取及降取濾波器，使其可進行任意符碼率的調整，達到連續可變符碼率收發機的效果，而透過降低符碼率連帶降低頻寬消耗並提升靈敏度來增強衛星通訊的可靠度。

    With the advancement of Low Earth Orbit (LEO) satellite communication technology, the Digital Video Broadcasting - Satellite - Second Generation (DVB-S2) has become an essential standard. This standard features excellent error correction capabilities and high spectral efficiency, allowing the system to operate even in low Signal-to-Noise Ratio (SNR) environments.
    This thesis focuses on the application of the DVB-S2 standard in satellite communication by designing and implementing a multi-symbol rate transceiver. Without adjusting the system sampling rate, we employ digital signal processing techniques, utilizing multi-stage two-times polyphase filters combined with a fractional-rate decimating Farrow Interpolator to implement variable up-sampling and down-sampling filters. This enables arbitrary symbol rate adjustments, realizing a continuously variable symbol rate transceiver. This approach effectively reduces the symbol rate, consequently decreasing bandwidth consumption and improving receiver sensitivity, thereby enhancing the reliability of satellite communications.

    摘要 i Abstract ii 誌謝 iii 目錄 iv 圖目錄 vii 表目錄 xiv 第一章、 緒論 1 1.1 研究動機與背景 1 1.2 章節簡介 1 第二章、 DVB-S2規格及收發機系統介紹 2 2.1 DVB-S2簡介及發射端流程圖 2 2.2 Stream Adaptation 3 2.2.1 Baseband Header Insertion 3 2.2.2 Padding 4 2.2.3 Baseband (BB) Scrambling 5 2.3 FEC (Forward Error Correction) Encoding 5 2.3.1 BCH Encoder (Outer Encoding) 6 2.3.2 LDPC Encoder (Inner Encoding) 7 2.3.3 Bit Interleaver 7 2.4 Bit Mapping 9 2.4.1 QPSK 9 2.4.2 8PSK 10 2.4.3 16APSK 11 2.4.4 32 APSK 12 2.5 Physical Layer (PL) Framing 13 2.5.1 Dummy PL Frame insertion 13 2.5.2 PL Signalling 14 2.5.3 Physical Layer (PL) Scrambling 15 2.6 Baseband Filter 17 2.6.1 Square-Root Raised Cosine (SRRC) Pulse Shaping Filter 18 2.6.2 Up-Sampling Filter 19 2.7 基頻接收端 20 2.7.1 Down-Sampling Filter 21 2.7.2 DVB-S2 Receiver 22 第三章、 可調式升取濾波器及降取濾波器 23 3.1 升取濾波器 23 3.1.1 Up-Sampling Half-Band Polyphase Filter 26 3.1.2 Farrow Interpolator 29 3.2 降取濾波器 32 3.2.1 Down-Sampling Half-Band Polyphase Filter 33 3.3 訊號模擬結果 34 3.3.1 SRRC Pulse Shaping Filter and Half-Band Polyphase Filters 34 3.3.2 訊號經升取及降取處理 37 第四章、 硬體架構與實現 46 4.1 AXI4-Stream溝通介面 46 4.2 降取濾波器架構 47 4.2.1 First Stage Down-Sampling Half-Band Polyphase Filter 49 4.2.2 Second to Fifth Down-Sampling Half-Band Polyphase Filters 53 4.2.3 Farrow 內插器 54 4.3 升取濾波器架構 59 4.3.1 平行兩路之Farrow內插器 60 4.3.2 Up-Sampling Half-Band Polyphase Filter 73 4.4 訊號模擬結果 77 第五章、 軟體定義無線電平台實現與驗證 81 5.1 軟體定義無線電(Software Defined Radio, SDR) 81 5.2 ZCU111 RFSoC平台 81 5.2.1 RF Data Converter 82 5.2.2 RFSoC Clock Stucture 88 5.2.3 RF-DAC/RF-ADC 基頻數位資料擺放 88 5.2.4 RF Data Converter設定介面 92 5.2.5 RFSoC平台使用流程 95 5.3 ZCU111平台驗證 96 5.3.1 硬體資源使用率及操作頻率 96 5.3.2 ZCU111平台自發自收實驗結果 100 5.3.3 靈敏度測量結果 113 第六章、 結論 124 參考文獻 125

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