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研究生: 鄭翊君
Yih-Chun Cheng
論文名稱: 應用於心電訊號感測壓縮之低複雜度可變尺寸正交多重匹配追蹤演算法之設計與實作
Low-Complexity Compressed Sensing with Variable Orthogonal Multi-Matching Pursuit and Partially Known Support for ECG Signals
指導教授: 蔡佩芸
Pei-Yun Tsai
口試委員:
學位類別: 碩士
Master
系所名稱: 資訊電機學院 - 電機工程學系
Department of Electrical Engineering
論文出版年: 2016
畢業學年度: 104
語文別: 中文
論文頁數: 116
中文關鍵詞: 壓縮感測技術心電訊號離散小波轉換正交匹配追蹤演算法多重正交匹配追蹤演算法
外文關鍵詞: Compressed Sensing (CS), Electrocardiogram (ECG), digital wavelet transform (DWT), orthogonal matching pursuit (OMP), orthogonal multi-matching pursuit (OMMP)
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  • 本論文中,我們提出了應用於無線體域網路(Wireless body sensor network)偵測心電訊號(Electrocardiogram, ECG)之低複雜度壓縮感測技術(Compressed Sensing, CS)。我們利用心電訊號在小波域(wavelet domain)上的特性來找出部分已知支持集合(partially known support set, PKS),以減少遞迴性貪婪還原演算法(greedy algorithm)估測與擴增步驟的運算量與複雜度。接著我們提出了可變尺寸之正交多重匹配追蹤演算法(variable orthogonal multi-matching pursuit, vOMMP),此演算法結合了正交匹配追蹤演算法(orthogonal matching pursuit, OMP)與多重正交匹配追蹤演算法(orthogonal multi-matching pursuit, OMMP)之優點。正交匹配追蹤演算法對於在遞迴運算之前段過程可確保搜尋到錯誤率極低的支持集合,維持還原的穩定性。而多重正交匹配追蹤演算法可減少遞迴次數且在遞迴運算的後段,能夠更廣泛的搜尋支持元素以補償前遞迴過程中的搜尋失誤,故更能夠有效的提升還原效能。除此之外,針對正交匹配追蹤相關的演算法最為複雜的運算為偽逆矩陣(pseudo inverse)的運算,我們提出了免反矩陣運算的還原方式,利用QR分解來避免反矩陣運算,相較於傳統求解壓縮感測訊號之正交匹配追蹤演算法,不僅有較低的複雜度,還可以有性能上的改善。實作上,我們用台積電90奈米製程實作。晶片面積(chip area)為 3.61〖mm〗^2 且 gate-count為308K。由晶片量測分析結果可知,在操作電壓0.9伏特且操作頻率為12MHz時,功耗為11.7mW。因此,我們的設計符合極高硬體使用效率,且達成WSBN的低功耗需求。


    We present low-complexity compressed sensing (CS) techniques for monitoring electrocardiogram (ECG) signals in wireless body sensor network (WBSN). First, we exploit ECG properties in the wavelet domain to extend the partially known support set (PKS) so as to reduce the support augmentation and estimation efforts in the iterative recovery algorithm. Then, variable orthogonal multi-matching pursuit (vOMMP) algorithm is proposed, using orthogonal matching pursuit (OMP) algorithm in the first phase to effectively augment the support set with reliable supports and adopting the orthogonal multi-matching pursuit (OMMP) in the second phase to rescue the missing support. Furthermore, the computation-intensive pseudo-inverse operation for signal reconstruction is simplified by the matrix-inversion-free technique based on QR decomposition. The performance and complexity comparisons manifest the advantages of our proposed techniques. The vOMMP MIF CS decoder is implemented in 90nm CMOS technology. The chip area is 3.61〖mm〗^2 and the gate-count is 308K gates. From the measurement result, the power consumption is 11.7 mW with supporting voltage at 0.9 V and operating clock at 12 MHz. Compared to prior chip implementations, our design shows good hardware efficiency and is suitable for low-energy applications.

    摘要 I Abstract II 目錄 III 圖示目錄 VI 表格目錄 X 第一章 緒論 1 1.1 研究動機 1 1.2 研究方法 1 1.3 論文組織 2 第二章 心電訊號壓縮感測技術相關知識介紹 3 2.1 應用於心電訊號的壓縮感測技術(CS-Based ECG Compression Algorithm) 4 2.2 壓縮感測演算法的分類 5 2.2.1 高斯隨機分佈感測(Gaussian random Sensing) 6 2.2.2 稀疏二元矩陣感測(Sparse Binary Sensing) 6 2.2.3 伯努利感測(Bernoulli Sensing) 7 2.3 心電訊號資料庫與效能指標(Performance Metrics)介紹 8 2.3.1 心電訊號資料庫 8 2.3.1 均方根誤差百分比(percentage root-mean-square difference, PRD) 9 2.3.2 訊號信雜比(signal to noise ratio, SNR) 10 2.4 壓縮演算法分類方法比較 10 第三章 傳統壓縮還原演算法 12 3.1 貪婪演算法 12 3.1.1 正交匹配追蹤演算法(OMP)[9][10] 12 3.1.2 正交多重匹配追蹤演算法(OMMP)[11] 14 3.1.3 壓縮採樣匹配追蹤演算法(CoSaMP)[4][12] 15 3.1.4 疊代硬閥值演算法(IHT)[4][13] 16 3.1.5 貪婪演算法比較與結論 18 第四章 部分已知集合輔助之可變尺寸正交匹配追蹤演算法(PKS-vOMMP) 19 4.1 部分已知集合的擴增 21 4.1.1 部分已知集合 21 4.1.2 基於小波轉換域之部分已知集合 22 4.2 可變尺寸正交匹配追蹤演算法 27 4.3 部分已知集合輔助之可變尺寸正交多重匹配演算法之流程介紹 30 4.3.1 初始化(Initial) 31 4.3.2 鑑定 (Identification) 31 4.3.3 擴增(Augmentation) 31 4.3.4 估測(Estimation) 32 4.3.5 更新殘餘量(Residual Update) 32 4.3.6 最佳K組解(K-term Approximation) 32 4.3.7 模式切換(Switching) 32 4.4 免反矩陣運算(Matrix Inversion Free)之還原演算法 33 4.5 模擬結果與討論 35 4.5.1 模擬參數設定 35 4.5.2 效能比較 37 4.5.3 時域訊號模擬結果呈現 42 4.5.4 運算複雜度比較 45 第五章 硬體設計與實現 49 5.1 硬體設計流程 49 5.2 硬體方塊圖 50 5.3 硬體架構 54 5.1.1 QR分解 55 5.1.2 反向代回求解(backward Substitution) 64 5.1.3 殘餘組成的估測(residual component estimation) 與線性相關性 (Correlation) 65 5.1.4 堆積排序(Heapsort) and最佳K組解( K-term approximation) 66 5.4 記憶體 70 5.5 量化方式 72 5.6 資料流 77 5.7 硬體實現結果 80 第六章 硬體實作 86 6.1 晶片實作流程 86 6.2 Gated Clock處理 91 6.3 合成結果 92 6.3.1 布局平面圖 92 6.3.2 RTL simulation 97 6.3.3 Gated-level pre-layout Simulation 97 6.3.4 Gated-level post-layout Simulation 97 6.3.5 LVS驗證結果 98 6.4 硬體實作結果與比較 99 6.4.1 晶片規格 99 6.4.2 晶片分析量測結果與比較 100 第七章 結論 103 參考文獻 104

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