| 研究生: |
林威岑 Wei-Tsen Lin |
|---|---|
| 論文名稱: |
Kalman Filtering應用於可適性載波同步系統之研究 Investigation of Kalman Filtering for Adaptive Carrier Synchronization |
| 指導教授: |
張大中
Dah-Chung Chang |
| 口試委員: | |
| 學位類別: |
碩士 Master |
| 系所名稱: |
資訊電機學院 - 通訊工程學系 Department of Communication Engineering |
| 畢業學年度: | 93 |
| 語文別: | 英文 |
| 論文頁數: | 73 |
| 中文關鍵詞: | 卡曼濾波器 、鎖相迴路 、可適性載波回復 |
| 外文關鍵詞: | QAM, Adaptive carrier synchronization, cable receiver, Kalman filter, phase-locked loop |
| 相關次數: | 點閱:5 下載:0 |
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本篇論文探討以Kalman Filtering演算法處理通訊系統中存在的載波相位同步問題。針對此問題,實務上的解決方法是在接收機端使用一載波同步系統來達成發射與接收端間載波相位的同步,傳統上使用一基於回授控制系統的鎖相迴路來實現載波同步系統,然而因其使用的迴路頻寬為固定,以致在載波回復系統的設計上常是必須在系統的收斂時間與穩態誤差間做一妥協,這對設計者而言亦是一挑戰。有別於傳統上使用鎖相迴路架構的載波同步作法,Kalman Filtering演算法可作為可適性載波同步系統的應用,採用此種架構的主要優點為使用一具可適性調整的迴路頻寬在系統的收斂時間與穩態誤差間取得較佳的妥協,另外透過將載波同步問題導入為一Kalman Filtering的演算法應用,載波同步系統的設計更可簡化為僅設定對系統模型與量測結果的預估誤差程度即可,而有別於傳統上採用的鎖相迴路在設計上需設定迴路中的各個參數值。
In this thesis, we study the adaptive carrier synchronization by using the Kalman filtering technique. Practically, such problem can be resolved by a carrier synchronization loop in the receiver. Conventionally, a feedback loop called the phase-locked loop (PLL) is used to implement the carrier synchronization loop. However, due to the fixed loop bandwidth, the design of a PLL always needs the acquisition time and steady-state phase tracking variation of the carrier recovery loop to be compromised and thus possesses a design challenge for designers.Instead a legacy approach based on the PLL structure, an alternative method is to use the Kalman filtering technique. The major advantage of the Kalman-based scheme over the conventional PLL one is the self-adaptation of loop bandwidth for better compromising the trade-off between fast acquisition and small steady-state phase tracking variation. Moreover, by modeling the carrier drift as a Kalman filtering problem, the design of carrier recovery loops can be further simplified to set the noise condition according to the underlying process model and observations rather than to specify each filter parameter as the conventional PLL requires.
[1]Loke Kun Tan et al., "A 70-Mb/s variable-rate 1024-QAM cable receiver IC with integrated 10-b ADC and FEC decoder," IEEE Journal of Solid State Circuits, vol. 33, No. 12, Dec. 1998.
[2]David A. Byan, "QAM for terrestrial and cable transmission," IEEE Transactions on Consumer Electronics, vol. 41, No. 3, pp.383-391, Aug. 1995.
[3]Donald R. Stephens, Phase-locked Loops for Wireless Communications: Digital, Analog and Optical Implementations, 2nd ed., Kluwer Academic Publishers, 2002.
[4]Chun-Nan Ke, Cheng-Yi Huang, and Chih-Peng Fan, "An adaptive carrier synchronizer for M-QAM cable receiver," IEEE Transactions on Consumer Electronics, vol. 49, No. 4, Nov. 2003.
[5]Patapoutian A., "On phase-locked loops and Kalman filters," IEEE Transactions on Communications, vol. 47, No. 5, pp.670-672, May 1999.
[6]Aghamohammadi A., Meyr H., and Ascheid G., "Adaptive synchronization and channel parameter estimation using an extended Kalman filter," IEEE Transactions on Communications, vol. 37, pp.1212-1219, Nov. 1989.
[7]Oren T. and Raphaeli D. "A new suppressed carrier synchronizer with reduced phase jitter for QAM systems," The 21st IEEE Convention of 11-12, April 2000.
[8]B.D.O Anderson and J.B. Moore, Optimal Filtering, Englewood Cliffs, New Jersey: Prentice-Hall, 1979.
[9]Heinrich Meyr, Marc Moeneclaey, Stefan A. Fechtel, Digital Communication Receivers: Synchronization, Channel Estimation, and Signal Processing, John Wiley & Sons, Inc., 1998.
[10]A. Leclert and P. Vandamme, "Universal carrier recovery loop for QASK and PSK signal sets," IEEE Transactions on Communications, vol. COM-31, No. 1, Jan. 1983.
[11]Robert L. Cupo, Richard D. Gitlin, "Adaptive carrier recovery systems for digital data communication receivers," IEEE Journal on Selected Areas on Communication, vol. 7, pp.1328-1339, Dec. 1989.
[12]L. Brecher, N. Sommer, E. Weinstein, "Analysis of lock-loss events in discrete-time phase locked loop (PLL)," Proceeding of the 11th IEEE International Conference on Electronics, pp.354-357, Dec. 2004.
[13]D. N. Godard, "Self-recovering equalizer and carrier tracking in two dimensional data communication system," IEEE Transactions on Communications, vol. COM-28, No. 11, pp.1867-1875, Nov. 1980.
[14]Floyd M. Gardner, "Interpolation in digital modems—part I: Fundamentals," IEEE Transactions on Communications, vol. 41, No. 3, March 1993.
[15]L. Erup, F. M. Gardner, and R. A. Harris, "Interpolation in digital modems—partⅡ: Implementation and performance," IEEE Transactions on Communications, vol. 41, No. 6, June 1993.
[16]Floyd M. Gardner, "A BPSK/QPSK timing-error detector for sampled receiver," IEEE Transactions on Communications, vol. 34, No. 5, pp. 423-429, May 1986.
[17]Ray Andraka, "A survey of CORDIC algorithms for FPGA based computers," Proceedings of the 1998 ACM/SIGDA sixth international symposium on field programmable gate arrays, pp. 191-200, 1998.
[18]Douglas J. Smith, HDL Chip Design: A practical guide for designing, synthesizing and simulation ASICs and FPGAs using VHDL or Verilog, Doone Publications, 1996.
[19]K. C. Chang, Digital Systems Design with VHDL and Synthesis: An Integrated Approach, IEEE Computer Society, 1999.
[20]Bob Zeidman, Verilog Designer’s Library, Upper Saddle River, New Jersey: Prentice-Hall, 1999.
[21]Memec Spartan-3 MB User’s Guide, v2.0, Memec Design, Sept. 2004.
[22]Memec P160 Prototype Module User’s Guide, v1.1, Memec Design, Nov. 2002.
[23]Acute PG-editor User Manual, Acute Technology Inc., Available: http://www.acute.com.tw
[24]Training Kit for the Agilent Technologies 16700-Series Logic Analysis System, Agilent Technologies, Aug. 2001.
[25]Memec P160 Analog Module User Guide, v1.2, Memec Design, July 2003.
[26]Agilent 54642D Mixed-Signal Oscilloscopes User’s Guide, Agilent Technologies, Sept. 2002.