近年來，半導體製程技術快速的發展。在半導體產業裡，元件特性的模擬經常被使用來降低製造的成本與時間。因此開發半導體元件 (如：金氧半場效電晶體、絕緣基板金氧半場效電晶體以及功率元件) 模擬的方法以及利用模擬方法來事先針對所設計的元件做模擬就變成相當重要的任務。首先我們對開發全模擬以及半模擬技術於設計功率元件進行研究，並針對矽覆絕緣側向式功率金氧半場效電晶體中基底偏壓對臨限電壓之影響作探討。
進而我們提出了Branch-cut 方法，說明Branch-cut是如何定義Kink 效應在SOI元件發生的機制。利用Branch-cut技術把元件電流操作分為兩區：(1)寄生雙載子電晶體電流區；(2)通道電流區。並且找到三種不同的案例來分析Kink 效應：(1)Body效應；(2)寄生雙載子電晶體效應；(3)合併效應。而我們更近一步用遮蔽氧化層SOI結構來抑制部分空乏型矽覆絕緣元件的寄生雙載子電晶體效應。
隨著半導體產業的發展，高功率元件經常被應用在許多電力電子方面。其形式基本上可分為垂直通道(vertical-channel)及橫向通道(lateral- channel)的結構。本論文我們主要探討橫向通道的功率元件，此結構以側向雙擴散金氧半電晶體(LDMOS)為代表。首先我們針對SOI PN二極體的崩潰電壓作一討論，利用SOI晶片提供較好的絕緣性及合併一半絕緣覆晶矽層(SIPOS, Semi-Insulating POly-crystalline Silicon)，其電性近似於低摻雜埋藏層(low-doped buried layer)，目 的是增加元件的崩潰電壓，並使用元件模擬軟體ISE-TCAD驗證之。另外我們也將半絕緣覆晶矽層應用於SOI LDMOS元件上，並模擬此結構的電特性，發現仍具有正常金氧半場效電晶體的導通特性及耐壓特性，這說明此結構是可行的。
本論文也對元件製程參數對崩潰電壓的影響做一探討，並建立有SIPOS結構側向功率元件的分析模型，此分析模型主要是計算元件表面電位及表面電場。此分析模型與數值模擬相吻合，並可利用該模型來幫助設計其他側向功率元件如SOI LDMOS及SOI LIGBT等元件。
此外，在論文中我們提出了一種新穎的矽覆絕緣結構，結構中有別於傳統的矽覆絕緣結構多了一層低摻雜埋藏層(Low Doping Buried Layer, LDBL)，該結構可解決電路設計者在使用矽覆絕緣元件時，基底偏壓對元件崩潰特性所造成的負面影響。並完整的分析了基底偏壓所產生的背部金氧半效應(Back Gate Metal-Oxide-Semiconductor effect)，進而對該層的厚度以及濃度做進一步探討，其中發現LDBL濃度並非主要影響基底偏壓效應的主要因素；而當LDBL厚度等於2.65 ?m時，元件對基底偏壓效應有最佳的抑制效果。

In the recent years, the semiconductor manufacturing technology proceeded at a very rapid pace. The simulation of device’s characteristics is always used to reduce the manufacturing cost and time in the semiconductor industry. Therefore, it is a very important task to investigate the simulation method and use the simulation tools to develop the design structure of devices. At first, we use the simulation tools to develop the “fully simulation method” and “half simulation method”, and to study the power devices. The threshold voltage influenced by the substrate bias on SOI LDMOSFET was discussed.
Furthermore, in the partially depleted (PD) SOI NMOSFET device, the floating body effect emerges due to the accumulation of excess holes in the neutral substrate region. The floating body effect will cause the current curve of kink effect in the saturation region. In this paper, we have discussed about the kink effect in different situations and the branch-cut method was used to separate the current component into two parts: (1) the parasitic BJT current, (2) the channel current, respectively. Then we find three different cases to analyze: (1) the body effect, (2) the parasitic BJT effect, (3) the combination effect. Furthermore, the partially covered oxide structure is used to suppress the parasitic BJT current without influencing the body effect. It can be proved that the kink effect has two different stages, the first kink effect and the second kink effect, respectively.
An analytical model is presented to determine the potential and electric field distribution along the semiconductor surface of new silicon-on-insulator (SOI) reduced surface field (RESURF) device. The SOI structure is characterized by a semi-insulating polycrystalline silicon (SIPOS) layer inserted between a silicon layer and a buried oxide. An improvement in the breakdown voltage due to the presence of the SIPOS shielding layer is demonstrated. Numerical simulations using ISETCAD are shown to support the analytical model.
Besides, an optimal design of a silicon-on-insulator (SOI) device structure to eliminate the back gate bias effect of the lateral double diffused metal-oxide-semiconductor field effect transistor (LDMOSFET) is presented and to improve breakdown voltage. The SOI structure was characterized by inserting an low doping silicon buried layer (LDBL) between the silicon layer and the buried oxide layer. The LDBL thickness is a key parameter that affects the strong inversion condition of the back MOS capacitor of the new SOI diode. The optimal LDBL thickness in the SOI diode was 2.65 ?m.

Chapter 1
[1]S. Maeda, Y. Yamaguchi, I. J. Kim, T. Iwamatsu, T. Ipposhi, S. Miyamoto, S. Maegawa, K. Ueda, K. Mashiko, Y. Inoue, T. Nishimura, and H. Miyoshi, “Analysis of delay time instability according to the operating frequency in field shield isolated SOI circuits,” IEEE Trans. Electron Devices, vol. 45, pp.1479-1486, 1998.
[2]S. Maeda, Y. Hirano, Y. Yamaguchi, T. Iwamatsu, T. Ipposhi, K. Ueda, K. Mashiko, S. Maegawa, H. Abe, and T. Nishimura, “Substrate-bias effect and source-drain breakdown characteristics in body-tied short-channel SOI MOSFET’s,” IEEE Trans. Electron Devices, vol. 46, pp.151-158, 1999.
[3]T. Iwamatsu, Y. Yamaguchi, Y. Inoue, T. Nishimura, and N. Tsubouchi, “CAD-compatible high-speed CMOS/SIMOX gate array using field- shield isolation,” IEEE Trans. Electron Devices, vol. 42, pp.1934-1939, 1995.
[4]T. Iwamatsu, Y. Yamaguchi, K. Ueda, K. Mashiko, Y. Inoue, and T. Hirao, “High-speed 0.5 mm SOI 1/8 frequency divider with body-fixed structure for wide range of applications,” in Ext. Abst. SSDM, PP.575, 1995.
[5]W. Chen, Y. Taur, D. Sadana, K. A. Jenkins, J. Sun, and S. Cohen, “Suppression of the SOI floating-body effects by linked-body device structure,” in Symp. VLSI Tech., pp. 92, 1996.
[6]J. B. Kuo, and Ker-Wei Su, 1998, CMOS VLSI ENGINEERING Silicon-on Insulator (SOI), Kluwer Academic Publishers.
[7]K. Kato, T. Wada, and K. Taniguchi, “Analysis of kink characteristics in silicon-on-insulator MOSFET’s using two-carrier modeling,” IEEE Trans. Electron Devices, vol. 32, pp.458-462, 1985.
[8]S. P. Edwards, K. J. Yallup, and K. M. D. Meyer, “Two-dimensional numerical analysis of the floating region in SOI MOSFET’s,” IEEE Trans. Electron Devices, vol. 35, pp.1012-1020, 1988.
[9]K. K. Young and J. A. Burns, “Avalanche-induced drain-source breakdown in silicon-on-insulator n-MOSFET’s,” IEEE Trans. Electron Devices, vol. 35, pp.426-431, 1988.
[10]M. Yoshimi, M. Takahashi, T. Wada, K. Kato, S. Kambayashi, M. Kemmochi, and K. Natori, “Analysis of the drain breakdown mechanism in ultra-thin-film SOI MOSFET’s,” IEEE Trans. Electron Devices, vol. 37, pp.2015-2021, 1990.
[11]J. R. Davis, A. E. Glaccum, K. Reeson, and P. L. F Hemment, “Improved subthreshold characteristics of n-channel SOI transistors,” IEEE Electron Device Letters, vol. 7, pp.570-572, 1986.
[12]J. G. Fossum, R. Sundaresan, and M. Matloubian, “Anomalous subtreshold current-voltage characteristics of n-channel SOI MOSFET’s,” IEEE Electron Device Letters, vol. 8, pp.544-546, 1987.
[13]M. Terauchi, M. Yoshimi, A. Murakoshi, and Y. Ushiku, “Supression of the floating-body effects in SOI MOSFETs by bandgap engineering,” in VLSI Sym. Dig. Tech. Papers, pp.35-36, 1995.
[14]J. P. Colinge, “Silicon-on-insulator technology: materials to VLSI,” Chapter 5, Kluwer Academic Publishers, 2004.
[15]C. C. Chang, “Improvement of 2-D and 3-D Semiconductor Device Simulation Using Equivalent-circuit Model,” Ph.D. dissertation, National Central University, Taiwan, 2006.
[16]H. K. Lim, and J. G. Fossum, “Threshold Voltage of Thin-Film Silicon-On-Insulator (SOI) MOSFET’s,” IEEE Trans. Electron Devices, Vol. 30, No. 10, pp. 1244-1251, Oct. 1983.
[17]K. K. Young, “Analysis of Conduction in Fully Depleted SOI MOSFET’s,” IEEE Trans. Electron Devices, Vol. 36, No. 3, pp. 504-506, March 1989.
[18]E. R. Worley, “Theory of the Fully Depleted SOS/MOS Transistor,” Solid State Electronics, Vol. 23, pp. 1107-1111, 1980.
[19]J. B. McKitterick, and A. L. Caviglia, “An Analytical Model for Thin SOI Transistors,” IEEE Trans. Electron Devices, Vol. 36, No. 6, pp. 1133-1138, June 1989.
[20]F. Balestra, M. Benachir, J. Brini, and G. Ghibaudo, “Analytical Models of Subthreshold Swing and Threshold Voltage for Thin- and Ultra-Thin-Film SOI MOSFET’s,” IEEE Trans. Electron Devices, Vol. 37, No. 11, pp. 2303-2311, Nov. 1990.
[21]Y. Inoue, Y. Yamaguchi, T. Yamaguchi, J. Takahashi, T. Iwamatsu, T. Wada, Y. Nishimura, T. Nishimura, and N. Tsubouchi, “Selection of Operation Mode on SOI/MOSFET’s for High-Resistivity Load Static Memory Cell,” SOI Conf. Dig., pp. 94-95, 1993.
[22]M. Haond, and M. Tack, “Rapid Electrical Measurements of Back Oxide and Silicon Film Thickness in an SOI CMOS Process,” IEEE Trans. Electron Devices, Vol. 38, No. 3, pp. 674-676, March 1991.
[23]J. B. Kuo, and Ker-Wei Su, 1998, CMOS VLSI ENGINEERING Silicon-on Insulator (SOI), Kluwer Academic Publishers, Chapter 4.
[24]H. K. Gummel, “A Self-consistent Iterative Scheme for One-dimensional Steady State Transistor Calculations,” IEEE Trans. Electron Devices, pp.455-465, 1964.
[25]ISE TCAD Manuals, release 8.5.
Chapter 2
[26]B. J. Baliga, “High Voltage Integrated Circuits,” IEEE Press, 1988.
[27]C. M. Liu, K. H. Lou, and J. B. Kuo, “77 K versus 300 K Operation: The Quasi-Saturation Behavior of a DMOS Device and its Fully Analytical Model,” IEEE Trans. Electron Devices, Vol. 40, No. 9, pp. 1636-1644, September 1993.
[28]E. Arnold, T. Letavic, and H. Bhimnathwala, “High-Temperature Off-State Characteristics of Thin-SOI Power Devices,” IEEE Electron Device Letters, Vol. 17, No. 12, pp. 557-559, December 1996.
[29]陳蓮春(2000)，電功率MOSFET應用技術，建興出版社。
[30]胡永昌(2001)，分離式元件市場與發展趨勢。元件科技雜誌，25期，94頁。
[31]U.S. Patent Nos. 4,975,751.
[32]U.S. Patent Nos. 5,091,336.
[33]B. J. Baliga, “Evolution of MOS-Bipolar Power Semiconductor Technology,” proceeding of the IEEE, Vol. 76, No. 4, 1988.
[34]M. J. Declerg, and J. D. Plummer, “Avalanche breakdown in high voltage DMOS devices,” IEEE Trans. Electron Devices, Vol. ED-23, pp.1-6, 1976.
[35]B. J. Baliga, M. S. Adler, P. V. Gray, and R. P. Love, “The Insulated Gate Rectifier (IGR): A New Power Switching Device,” IEDM Technical Digest, pp.264-265, Dec. 1982.
[36]J. P. Russel, A. M. Goodman, L. A. Goodman, and J. M. Neilson, “The COMFET-A New High Conductance MOS-Gated Devices,” IEEE Electron Device Letters, Vol. ED-4, No. 3, pp.63-65, March 1983.
[37]B. J. Baliga, M. S. Adler, P. V. Gray, R. P. Love, and N. D. Zomer, “The Insulated Gate Transistor: A New Three-Terminal MOS-Controlled Bipolar Power Device,” IEEE Trans. Electron Devices, Vol. ED-31, No. 6, pp.821-828, June 1984.
[38]B. J. Baliga, “Trends in Power Semiconductor Devices,” IEEE Trans. Electron Devices, Vol. 43, pp.1717-1731, 1996.
Chapter 3
[39]C. M. Snowden, 1986, Introduction to Semiconductor Device Modelling, World Scientific, Chapter 4.
[40]Y. T. Tsai, , and T. C. Ke, “Electrode Separation Method to the Boundary Condition for a-Si TFT Mixed-level Simulation,” International Journal of Numerical Modelling: Electronic Networks, Devices, and Fields, Vol. 11, No. 2, pp. 123-130, 1998.
[41]Y. T. Tsai, C. Y. Lee, and M. K. Tsai, “Levelized Incomplete LU Method and Its Application to Semiconductor Device Simulation,” Solid-State Electronics, Vol. 44, No. 6, pp. 1069-1075, 2000.
[42]Y. T. Tsai, C. F. Dai, and M. K. Tsai, “An Improved Levelized Incomplete LU Method And Its Application to 2D Semiconductor Device Simulation,” Journal of Chinese Institute of Engineers, Vol. 24, No. 3, pp. 389-396, 2001.
[43]K. Kato, T. Wada, and K. Taniguchi, “Analysis of Kink Characteristics in Silicon-on-insulator MOSFETs Using Two-carrier Modeling,” IEEE Trans. Electron Devices, Vol. 32, No. 2, pp. 458-462, 1985.
[44]S. P. Edwards, K. J. Yallup, and K. M. D. Meyer, “Two-dimensional Numerical Analysis of the Floating Region in SOI MOSFETs,” IEEE Trans. Electron Devices, Vol. 35, No. 7, pp. 1012-1020, 1988.
[45]K. K. Young, and J. A. Burns, “Avalanche-induced Drain-source Breakdown in Silicon-on-insulator n-MOSFETs,” IEEE Trans. Electron Devices, Vol. 35, No. 4, pp. 426-431, 1988.
[46]M. Yoshimi, M. Takahashi, T. Wada, K. Kato, S. Kambayashi, M. Kemmochi, and K. Natori, “Analysis of the Drain Breakdown Mechanism in Ultra-thin-film SOI MOSFETs,” IEEE Trans. Electron Devices, Vol. 37, No. 9, pp. 2015-3021, 1990.
[47]J. R. Davis, A. E. Glaccum, K. Reeson, and P. L. F. Hemment, “Improved Subthreshold Characteristics of N-channel SOI Transistors,” IEEE Electron Device Letters, Vol. 7, No. 10, pp. 570-572, 1986.
[48]J. G.. Fossum, R. Sundaresan, and M. Matloubian, “Anomalous Subtreshold Current-voltage Characteristics of N-channel SOI MOSFETs,” IEEE Electron Device Letters, Vol. 8, No. 11, pp. 544-546, 1987.
[49]C. H. Ho, C. C. Chang, S. J. Li, and Y. T. Tsai, “The Branch-Cut Method and Its Applications in Two-Dimensional Device Simulation,” ACTA International Journal of Modelling and Simulation, Vol. 29, No. 1, pp. 1-6, 2009.
[50]J. P. Colinge, 2004, Silicon-on-insulator Technology: Materials to VLSI, Kluwer Academic Publishers, Chapter 5.
[51]J. Tihani, and H. Schlotterer, “Properties of ESFI MOS Transistors Due to the Floating Substrate and the Finite Volume,” IEEE Trans. Electron Devices, Vol. 22, No. 11, pp. 1017-1023, 1975.
[52]J. Colinge, “Reduction of Kink Effect in Thin-film SOI MOSFETs,” IEEE Electron Device Letters, Vol. 9, No. 2, pp. 97-99, 1988.
[53]J. B. Kuo, and S. C. Lin, 2001, Low-voltage SOI CMOS VLSI Devices and Circuits, John Wiley & Sons, Inc., Chapter 2.
[54]G. G. Shahidi, “SOI Technology for the GHz Era,” IBM Journal of Research and Development, Vol. 46, No. 2, pp. 121-131, 2002.
Chapter 4
[55]S. Merchant, E. Arnold, H. Baumagart, S. Mukherjee, H. Pein, and R. Pinker, “Realization of High Breakdown Voltage (>700 V) in Thin SOI Devices,” Proc. IEEE Int. Symp. Power Semiconductor Devices and IC’s, pp. 31-35, 1991.
[56]S. K. Chung, S. Y. Han, J. C. Shin, Y. I. Choi, and S. B. Kim, “An Analytical Model for Minimum Drift Region Length of SOI RESURF Diodes,” IEEE Electron Device Letters, Vol. 17, pp. 22-24, 1996.
[57]Z. Sun, W. Sun, and L. Shi, “Modeling Kirk Effect of RESURF LDMOS,” Solid-State Electronics, Vol. 49, pp.1896-189, 2005.
[58]Y. S. Huang, and B. J. Baliga, “Extension of RESURF Principle to Dielectrically Isolated Power Devices,” Proc. IEEE Int. Symp. Power Semiconductor Devices and IC’s, pp. 27-30, 1991.
[59]S. Merchant, E. Arnold, H. Baumagart, R. Egloff, T. Letavic, S. Mukherjee, and H. Pein, “Dependence of Breakdown Voltage on Drift Length and Buried Oxide Thickness in SOI RESURF LDMOS Transistors,” Proc. IEEE Int. Symp. Power Semiconductor Devices and IC’s, pp. 124-128, 1993.
[60]D. Jaume, G. Charitat, J.M. Reynes, and P. Russel, “High-voltage Planar Devices Using Field Plate and Semi-resistive Layers,” IEEE Trans. Electron Devices, Vol. 38, pp. 1681-1684, 1991.
[61]T. Matsushita, T. Aoki, T. Otsu, H. Yamoto, H. Hayashi, M. Okayama, and Y. Kawana, “Semi-insulating Polycrystalline-Silicon (SIPOS) Passivation Technology,” Jpn. J. Appl. Phys., Vol. 15, pp. 35-40, 1976.
[62]A. Nakagawa, Y. Yamaguchi, N. Yasuhara, K. Hirayama, and H. Funaki, “New High Voltage SOI Device Structure Eliminating Substrate Bias Effects,” IEDM Tech. Dig., pp. 477-480, 1996.
[63]ISE TCAD Manuals, release 9.5.
[64]T. Stockmeier, and K. Lilja, “SIPOS-passivation for High Voltage Power Devices with Planar Junction Termination,” Proc. IEEE Int. Symp. Power Semiconductor Devices and IC’s, pp. 145-148, 1991.
[65]S. Mukherjee, C. J. Chou, K. Shaw, D. McArthur, and V. Rumennik, “The Effect of SIPOS Passivation on DC and Switching Performance of High Voltage MOS Transistors,” IEDM Tech. Dig., pp. 646-649, 1986.
[66]T. Sakai, K. C. So, Z. Shen, and T. P. Chow, “Modeling and Characterization of SIPOS Passivated, High Voltage, N- and P-channel Lateral RESURF type DMOSFETs,” IEEE Int. Symp. Power Semiconductor Devices and IC’s, pp. 288-292, 1992.
[67]S. K. Chung, and S. Y. Han, “Analytical Model for the Surface Field Distribution of SOI RESURF Device,” IEEE Trans. Electron Devices, Vol. 45, pp. 1374-1376, 1998.
[68]R. A. Kokosa, R. L. Davies, “Avalanche Breakdown of Diffused Silicon P-N Junction,” IEEE Trans. Electron Devices, Vol. 13, pp. 874-881, 1966.
[69]R. V. Overstraeten, H. D. Man, “Measurement of the Ionization Rates in Diffused Silicon P-N Junctions,” Solid-State Electronics, Vol. 13, pp. 583-608, 1970.
[70]W. Fulop, “Calculation of Avalanche Breakdown Voltages of Silicon P-N Junction,” Solid-State Electronics, Vol. 10, pp. 39-43, 1967.
[71]S. K. Chung, D. K. Shin, “An Analytical Model for Interaction of SIPOS Layer with Underlying Silicon of SOI RESURF Devices,” IEEE Trans. Electron Devices, Vol. 46, pp. 1804-1807, 1999.
Chapter 5
[72]S. Merchant, E. Arnold, H. Baumagart, S. Mukherjee, H. Pein, and R. Pinker, “Realization of High Breakdown Voltage (>700 V) in Thin SOI Devices,” Proc. IEEE Int. Symp. Power Semiconductor Devices and IC’s, pp. 31-35, 1991.
[73]S. K. Chung, S. Y. Han, J. C. Shin, Y. I. Choi, and S. B. Kim, “An Analytical Model for Minimum Drift Region Length of SOI RESURF Diodes,” IEEE Electron Device Letters, Vol. 17, pp. 22-24, 1996.
[74]Z. Sun, W. Sun, and L. Shi, “Modeling Kirk Effect of RESURF LDMOS,” Solid-State Electronics, Vol. 49, pp.1896-189, 2005.
[75]Y. S. Huang, and B. J. Baliga, “Extension of RESURF Principle to Dielectrically Isolated Power Devices,” Proc. IEEE Int. Symp. Power Semiconductor Devices and IC’s, pp. 27-30, 1991.
[76]S. Merchant, E. Arnold, H. Baumagart, R. Egloff, T. Letavic, S. Mukherjee, and H. Pein, “Dependence of Breakdown Voltage on Drift Length and Buried Oxide Thickness in SOI RESURF LDMOS Transistors,” Proc. IEEE Int. Symp. Power Semiconductor Devices and IC’s, pp. 124-128, 1993.
[77]C. H. Ho, C. N. Liao, F. T. Chien, and Y. T. Tsai, “An Analytical Model for Silicon-on-Insulator Reduced Surface Field Devices with Semi-Insulating Polycrystalline Silicon Shielding Layer,” Japanese Journal of Applied Physics, Vol. 47, No. 7, pp. 5369-5373, 2008.
[78]A. Nakagawa, Y. Yamaguchi, N. Yasuhara, K. Hirayama, and H. Funaki, “New High Voltage SOI Device Structure Eliminating Substrate Bias Effects,” IEDM Tech. Dig., pp. 477-480, 1996.
[79]D. W. Tong, J. L. Benjamin, and W. R. V. Dell, “Interface Effects of SIPOS Passivation,” IEEE Trans. Electron Devices, Vol. 33, pp. 779-787, 1986.
[80]S. M. Sze, 1981, Physics of Semiconductor Devices 2nd edn, New York: Wiley.
Chapter 6
[81]C. H. Ho, and Y. M. Hsin, “The Process Integration of GaN BJT and MOSFET,” Electron Devices and Materials Symposium, 2005, Kaohsiung, Taiwan.
[82]W. C. Lai, M. Yokoyama, C. C. Tsai, C. S. Chang et al., “Electrical Properties of Multiple High-Dose Si Implantation in p-GaN,” Japanese Journal of Applied Physics, Vol. 38, pp. L802-L804, 1999.
[83]Y. Irokawa, Y. Nakano, M. Ishiko, T. Kachi et al., “MgO/p-GaN Enhancement Mode Metal-oxide Semiconductor Field-effect Transistor,” Applied Physics Letters, Vol. 84, No. 15, pp. 2919-2921, 2004.