近幾年來，在高品質影像顯示及高容量資料單元傳送的需求性日益高漲的時代，HDMI 、SATA 及USB3.0等Gb/s 等級的高速串列訊號介面開始普遍應用在3C產業界。但在進入Gb/s傳輸世代後，完整傳輸路徑上的負載，對低電壓及低時脈週期訊號傳輸品質的影響性大幅提升。如何在矽前(Pre-silicon)開發階段就能夠掌握產品在高速差動訊號品質，是值得探討並克服的議題。
在本論文中，首先訂定出 PSFTE 的流程，透過三個階段的模擬分析，在矽前階段進行從晶片到遠端各個不同測試點的訊號品質。再利用信號擺幅控制法，依據不同的完整傳輸路徑進行調變，讓輸出訊號品質達成最佳化。除了可以避免IC在矽後驗證時，因為信號品質的不良，衍生出因為改版所造成的額外成本支出，最重要的因為改版所造成產品上市時間的延遲，可能會造成更大的商業損失。

In the recent years, as the High definition video and bulk size format data transfer became popular, the Gb/s level high speed differential transmission signals like HDMI, SATA and USB3.0 are instead of the traditional style became more popular in 3C market. The newest generation transmission interface had been developed for this requirement In the Gb/s high speed, these loadings became the major factors for signal integrity. How to estimate the signal integrity of high speed differential pairs is more important for real product in Pre-silicon full-transmission evaluation.
In this paper, we defined the PSFTE flow to simulate and analyze the signal integrity from die to far-end in Pre-silicon stage. Then we can use amplitude adjustment method to optimize the signal integrity for different full transmission line. It can avoid not only the extra cost from the version change, the most important is the timing delay will cause more business loss.

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