為了縮短類比積體電路的設計時間，類比積體電路的自動化設計，也慢慢的受到重視。然而，由於深次微米效應的影響，在方程式基礎的方法中對於電晶體參數的預估往往存在很大的誤差，這造成了電路效能的預估不夠精確，因此需要數個迴圈重覆修正，而本論文便是採用gm/ID的概念來解決此問題。由於gm/ID與電晶體大小無關，因此只需要使用偏壓及電流作為變數，便能夠精確地預估電路的效能，在整體設計的效率及精確度都有很大的改善。
除此之外，本論文加入了寄生效應的考量來增加預估電路效能的精確度，每顆電晶體的通道長度也變成能讓使用者自行決定的變數。整個自動化流程以MATLAB實現，從實驗結果可看出整體的低頻增益、相位邊限以及單一增益頻寬皆得到較小的誤差值。另外，由於通道長度為可變動之參數，故最後設計出來的電路面積也能較先前的方法所得到的設計來的小。

In order to shorten the design cycles of analog circuits, analog design automation has become a popular research topic. However, due to the deep-submicron effects, the estimated transistor parameter often exist errors in the equation-based approaches. This results in wrong prediction of circuit performance and leads to several redesign cycles to meet the specifications. In this thesis, the gm/ID design concept is adopted to solve this problem. Because gm/ID is an independent value to the device size, only internal bias voltages and currents are required to predict circuit performance, which greatly improves the overall efficiency and accuracy.
In addition, this thesis also considers the parasitic effects to improve the accuracy of estimating the circuit performance. The channel length of each transistor also becomes a flexible variable to provide more choices to users. The entire automation process has been implemented in MATLAB environment. According to the experimental results, the prediction errors of overall low-frequency gain, phase margin and unity gain bandwidth are successfully reduced. In addition, because the channel length of some transistors can be adjusted, the circuit areas are smaller than the designs generated in previous approach.

[1] F. El-Turky and E.E. Perry, BLADES: an arrificial intelligence approach to analog circuit design",IEEE Trans. on CAD, Vol. 8, No. 6,1989, pp. 680-692.
[2] S. Kirkpatrick, C. D. Gelatt Jr., and M. P. Vecchi, “Optimization by Simulated Annealing”, Science, vol. 220, no. 4598, pp. 671-680, May 1983.
[3] C.-W. Lin, P.-D. Sue, Y.-T. Shyu and S.-J. Chang, “A Bias-Driven Approach for Automated Design of Operational Amplifiers”, in Proc. Int’l Symp. on VLSI Design, Automation, and Test, pp 119-121, 2009.
[4] P. Mandal, V. Visvanathan, “CMOS Op-Amp Sizing Using a Geometric Programming Formulation”, IEEE Trans. on Computer-Aided Design, vol. 20, no. 1, pp. 22-38, Jan. 2001.
[5] M. del M. Hershenson, S. P. Boyd, and T. H. Lee, “Optimal Design of a CMOS Op-Amp via Geometric Programming”,IEEE Trans. on Computer-Aided Design, vol. 20, no. 1, pp. 1-21, Jan. 2001.
[6] J. Kim, J. Lee, L. Vandengerghe, C. Yang, “Techniques for Improving the Accuracy of Geometric-Programming Based Analog Circuit Design Optimization,” in Proc. Int’l Conf. on Computer-Aided Design, pp. 863-870, 2004.
[7] V. Aggarwal, U. O’Reilly, “Simulation-Based Reusable Posynomial Models for MOS Transistor Parameters,” in Proc. Design, Automation and Test in Europe, pp. 69-74, 2007.
[8] W. Gao and R. Hornsey, “A Power Optimization Method for CMOS Op-Amps Using Sub-Space Based Geometric Programming”, in Proc. Design, Automation and Test in Europe, pp. 508-513, 2010.
[9] 詹立宇,“可改善幾何演算法之精準度的電壓趨動運算放大器自動化設計方法,” 國立中央大學電機工程研究所碩士論文, July 2011
[10] F. Silveira, D. Flandre, P.G.A. Jespers, ” A gm/ID based methodology for the design of CMOS analog circuits and its application to the synthesis of a silicon-on-insulator micropower OTA,” IEEE J. Solid-State, vol. 31, no. 9, 1996, pp. 1314-1319.
[11] M. S. Bazarar, H. D. Sherali, and C. M. Shetty, “Nonlinear Programming,” Wiley, 1993, 2nd ed.
[12] H. Dammak, S. Bensalem, and M. Loulou, “Design of Folded Cascode OTA in Different Regions of Operation Through gm/ID Methodology,” World Academy of Science,Engineering and Technology, 2008
[13] Takayuki KONISHI, Kenji INAZU, Jun Gyu LEE, Masanori NATSUI, Shoichi MASUI, Boris MURMANN ,” Design Optimization of High-Speed and Low-Power Operational Transconductance Amplifier Using gm/ID Lookup Table Methodology”, IEICE TRANSACTIONS on Electronics Vol.E94-C No.3 pp.334-345
[14] Binkley, D.M., "Tradeoffs and Optimization in Analog CMOS Design", Mixed Design of Integrated Circuits and Systems, 2007, pp. 47-60
[15] Sedra/Smith, Microelectronic Circuits, Oxford University Press, 2003
[16] M. Loulou, S. Ait Ali, M. Fakhfakh, N. Masmoudi, “An optimized methodology to design CMOS operational amplifier,” IEEE International Conference on Microelectronics, 2002, pp. 14-17.