| 研究生: |
薛宇廷 Yu-ting Hsueh |
|---|---|
| 論文名稱: |
應用於醫療裝置無線通訊服務頻帶之開迴路調變頻率合成器 A Frequency Synthesizer with Open-Loop BFSK Modulation for Medical Device Radiocommunications Service (MedRadio) Band |
| 指導教授: |
薛木添
Muh-Tian Shiue |
| 口試委員: | |
| 學位類別: |
碩士 Master |
| 系所名稱: |
資訊電機學院 - 電機工程學系 Department of Electrical Engineering |
| 畢業學年度: | 99 |
| 語文別: | 中文 |
| 論文頁數: | 85 |
| 中文關鍵詞: | 調變 、無線通訊服務頻帶 、頻率合成器 |
| 外文關鍵詞: | Medical Device Radiocommunications Service (MedR, Modulation, Frequency Synthesizer |
| 相關次數: | 點閱:9 下載:0 |
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在2009年美國聯邦通訊委員會制定了一個工作頻率範圍在401~406MHz的無線頻帶供作醫療裝置無線通訊服務,其中402~405MHz是植入式醫療裝置所使用的範圍,401~402MHz和405~406MHz是穿戴式醫療裝置所使用的範圍。其應用的範圍適合在具有極低功耗和在短距離下有更快速的資料傳輸速度的完全積體化之人體植入式電子輔具。
本論文設計了一個應用於植入式視覺輔具之開迴路調變頻率合成器,並提出一種新架構的調變方法,能有低電路複雜度和快速資料傳輸速度的優點,那是使用開迴路系統架構和在迴路濾波器與壓控振盪器中間加入一組類比加法器,藉由改變類比加法器的控制開關而直接改變壓控振盪器所需的控制端電壓以達到直接調變的方式。在壓控振盪器的設計,利用降低金屬繞線電感之寄生電阻而增加品質因素以及使用可調電容來降低壓控振盪器KVCO值的方式來改善壓控振盪器的相位雜訊。
最後使用TSMC 0.18μm 1P6M CMOS標準製程來實現此開迴路調變頻率合成器,工作電壓為1.5V,晶片面積為1.995 mm2。在佈局的模擬結果可以看到壓控振盪器的相位雜訊在距離載波160kHz處為-106.7dBc/Hz,總可調範圍為85MHz;而調變頻率合成器鎖定時間小於50μs,消耗功率為2.89mW,資料傳輸速度可達1Mbps。
In 2009, the US Federal Communication Commission (FCC) announced that Medical Device Radiocommunication Service (MedRadio) band is in the range of 401-406MHz, where 402-405MHz band is for medical implant devices, and 401-402MHz and 405-406MHz bands are for usages of medical body-worn devices. The application of MedRadio band is suitable for fully integrated human implantable prostheses with ultra-low power consumption and higher data rate in a short distance.
In order to implement an available frequency synthesizer with open-loop BFSK modula-tion for implantable visual prostheses, this thesis mainly proposes a new modulation circuit that features low complexity and high data rate. Using open-loop modulation with an analog adder to the LPF before the VCO, the proposed circuit achieves the mechanism of direct modulation by switching input the voltage level of the analog adder to adjust the input voltage of the VCO. Besides, the design of VCO reduces parasitic resistance of metal spiral inductor and lowers the KVCO of VCO to improve the phase noise of VCO.
The designed circuits in this thesis are implemented in TSMC 0.18 μm standard CMOS process with 1.5V supply voltage, and the chip area is 1.995 mm2. The post-layout-simulation results show that -106.7 dBc/Hz of VCO phase noise at 160 kHz offset, less than 50 μs of locking time, 2.89 mW of power consumption, and 1 Mbps of data rate are achieved in the designed frequency synthesizer.
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