近年來，可攜式電子產品為了獲得消費者的青睞，其必須整合各式各樣的功能，因此為了增加電池的使用時間，系統會依產品的使用情形切換到不同模式，同時也必須具備好的轉換效率。故對於電源管理IC而言，為了應付如此頻繁且快速的模式切換，因此必須要在模式切換的暫態瞬間，快速的反應以提供負載電源，所以暫態反應速度將是一項重要的規格。而傳統的電壓或電流模式因為迴路補償造成頻寬較窄，其暫態響應的速度較慢，故本論文將採用漣波控制中的電壓模式磁滯控制作為基本的架構，其具有快速的暫態響應與簡單的架構。
　　然而，此種磁滯控制會因為電路中的傳遞延遲造成輸出電壓無法在一開始所預設的磁滯視窗裡震盪，也造成輸出電壓的漣波較大，因此本論文將提出具適應性漣波控制器來改善這個問題。另外也針對電路啟動初期，電感電流會一下子就超過功率電晶體的上限，造成較大的過充電壓做討論，而這裡將使用切換功率電晶體的方式以達到降低過充電壓的現象。
　　本論文所實現之電路，是以TSMC 0.35um (5V) CMOS 製程來實現傳統電壓模式磁滯控制的降壓型轉換器，其輸入電壓為3.4V~5V，輸出電壓為0.7V~2.5V，輸出的負載電流範圍為50mA~600mA，最高的轉換效率可達92.7%。而使用具適應性漣波控制器後，以輸入電壓為5V，輸出電壓為2.5與1V且設定磁滯視窗上下限為20mV為例，皆可以讓輸出電壓穩定的震盪在所預設的磁滯視窗內。

　　In recent years, the portable electronic products must integrate a wide range of functions to obtain the favor of consumers, so in order to extend the battery life time, the system will switch to different mode according to the usage of the product, and also need good efficiency. Therefore, the power management IC should have fast transient response to provide the loading current, because copes with such frequent and rapid mode switching. Furthermore, the conventional voltage or current mode because the loop compensation resulting in bandwidth is narrow, its slow transient response. This thesis will use the hysteretic voltage-mode control of buck converter which has a fast transient response and simple structure.
　　However, due to the propagation delay the output voltage cannot oscillate the pre-defined hysteresis window, also cause the output voltage ripple larger. Therefore, the thesis proposes an adaptive ripple controller to improve this problem. And during the start-up period, the inductor current will raise beyond the current limit of the power switches for a short time; we use the method of selecting two P-type power switches.
　　The conventional hysteretic voltage-mode control of buck converter is implemented with TSMC 0.35um (5V) CMOS process. In the proposed buck converter, the input voltage is 3.4V ~5V, the output voltage is 0.7V~2.5V, the loading current is from 50mA ~600mA, and the highest efficiency is 92.7%. This circuit with adaptive ripple controller can generate a virtual window for hysteretic comparator such that the sawtooth signal of output voltage is controlled to be within the given window, when the input voltage is 5V, output voltage is 1V or 2.5V and the pre-defined window is 20mV for example.

[1] C.-I. Chiu, “On the implementation of an ultra-wide-load high-efficiency DC-DC buck converter,” MS Thesis, Department of Electrical Engineering, National Central University,2011.
[2] F. Su, W.-H. Ki, and C.-Y. Tsui, ”Ultra fast fixed-frequency hysteretic buck converter with maximum charging current control and adaptive delay compensation for DVS applications,” IEEE J. Solid-State Circuits, vol.43, no.4, pp.815-822, Apr. 2008.
[3] R. J. Milliken, J. Silva-Martinez, and E. Sanchez-Sinencio, “Full on-chip CMOS low-dropout voltage regulator,” IEEE Trans. Circuits and Systems I, vol.54, no.9, pp.1879-1890, Sep. 2007.
[4] J. A. Starzyk, Y.-W. Jan, and F. Qiu, ”A DC–DC charge pump design based on voltage doublers,” IEEE Trans. Circuits and Systems I, vol. 48, no.3, pp.350-359, Mar. 2001.
[5] C. F. Lee and P. K. T. Mok, “A monolithic current-mode CMOS DC-DC converter with on-chip current-sensing technique,” IEEE J. Solid-State Circuits, vol.39, no.1, pp.3-14, Jan. 2004.
[6] J. Xiao, A.V. Peterchev, J. Zhang, and S.R. Sanders, “A 4-uA quiescent-current dual-mode digitally controlled buck converter IC for cellular phone applications,” IEEE J. Solid-State Circuits, vol.39, no.12, pp.2342-2348, Dec. 2004.
[7] R. W. Erickson and D. Maksimovic, Fundamentals of power electronics, 2nd edition, John Wiley, New York, 1950.
[8] W.-C. Chen, “Reduction of equivalent series inductor effect in delay-ripple reshaped constant on-time control for buck converter with multi-layer ceramic capacitors, ” MS Thesis, Institute of Electrical Engineering National Chiao-Tung University, 2012.
[9] R. Redl and J. Sun, “Ripple-based control of switching regulators an overview,” IEEE Tran. Power Electron., vol.24, no.12, pp.2669-2680, Dec. 2009.
[10] P. Li, D. Bhatia, L. Xue, and R. Bashirullah , ”A 90–240 MHz hysteretic controlled DC-DC buck converter with digital phase locked loop synchronization,” IEEE J. Solid-State Circuits, vol.46, no.9, pp.2108-2119, Sep. 2011.
[11] R. Redl and G. Reizik, “Switched noise filter for the buck converter using the output ripple as the PWM ramp,” Proc. of IEEE APEC, 2005.
[12] F. Su and W.-H. Ki, “Digitally assisted quasi-V2 hysteretic buck converter with fixed frequency and without using large-ESR Capacitor,” IEEE International Solid-State Circuits Conference, pp.446-447,447a, Feb. 2009.
[13] T. Nabeshima, S. Yoshida, S. Chiba, and K. Onda, ”Analysis and design considerations of a buck converter with a hysteretic PWM controller,” Proc. of IEEE Power Electronics Specialists Conference, 2004.
[14] C. Song, “Accuracy analysis of constant-on current-mode DC-DC converters for powering microprocessors,” Proc. of IEEE APEC, 2009.
[15] P. E. Allen and D. R. Holberg, CMOS Analog Circuit Design, 2nd edition, Oxford University Press, 2002.
[16] R. J. Baker, CMOS Circuit Design, Layout, and Simulation, 3rd edition, IEEE Press,2010.
[17] J. Shieh, M. Patil, and B.J. Sheu, “Measurement and analysis of charge injection in MOS analog switches,” IEEE J. Solid-State Circuits, vol.22, no.2, pp.277-281, Apr. 1987.
[18] TI datasheet, “LF398: Application note 775 specifications and architectures of sample-and-hold amplifiers,” 1998.
[19] H.-Y. Luo, ”Automatic synthesis flow of DC to DC step-down converter circuit,” MS Thesis, Department of Electrical Engineering, National Central University, 2011.
[20] C.J. Chuang and H. P. Chou, “An efficient fast response hysteresis buck converter with adaptive synthetic ripple modulator,” Proc. of Int’l Conference on Power
Electronics, May 2011.
[21] H. H. Ko, “A high efficiency synchronous CMOS switching buck regulator with accurate current sensing technique,” MS Thesis, Department of Electrical Engineering, National Central University, 2007.