近年來正交分頻多工(OFDM)系統被廣泛的應用在各式無線通訊系統上，主要其優點為有效對抗符元間干擾(Inter-Symbol Interference)與頻率選擇性衰減的影響。其中快速傅立葉轉換(FFT)處理器為實現正交分頻多工系統的核心，因此在本論文中，將設計與實現一個低複雜度及高效率並可適用於多種OFDM標準系統之快速傅立葉轉換處理器，由於不同正交分頻多工的系統具有相似的硬體架構，藉由增加些許硬體以提高此FFT處理器之利用性。在演算法上，採用Radix-22與Winograd Fourier Transform Algorithm (WFTA) 演算法為基礎且使用單一路徑延遲回授(SDF)之管線架構實現。另外，旋轉因子(Twiddle Factor)的乘法以座標軸數位旋轉計算器(CORDIC)取代複數乘法器。架構中所需用到之記憶體以FPGA內部記憶體(Block Memory)來實現，達到節省硬體資源的目的。最後透過Xilinx Virtex-4 XC4VLX160來實現3780、8192、4096、2048點的快速傅立葉轉換處理器。

In now days, Orthogonal Frequency Division Multiplexing, (OFDM) has been widely adapted in wireless communication to effectively overcome the Inter-Symbol Interference and Frequency Selective Fading Fast Fourier Transform (FFT) is the core technique in achieves Orthogonal Frequency Division Multiplexing, OFDM. In this thesis, we designed and created a low-complex and high performance FFT which can suitable in multiple OFDM standard systems.
Due to different OFDM system has similar hardware framework, by raise up hardware to increase utilization of FFT. We adapt Radix-22 and Winograd Fourier Transform Algorithm as foundation and use Single-Path Delay Feedback (SDF) of pipeline-based architecture. Using CORDIC of Twiddle Factor to replace complex multiplexer. Hence, we try to attain decease hardware workload by introducing FPGA Block Memory. Finally, thru Xilinx Virtex-4 XCVLX160 to accomplish 3780、8192、4096、2048 Fast Fourier Transform.

[1] ETSI, “Digital Video Broadcasting (DVB)；Framing structure, Channel coding and Modulation for Digital Terrestrial Television,” ETSI EN 300 744 v1.5.1,2004
[2] GB 20600-2006, Framing Structure, Channel Coding and Modulation for Digital Television Terrestrial Broadcasting System, Chinese National Standard, 2006.
[3] Yang Xu-xia, GUI Lin, YU Song-yu, “Study of 3780-point FFT processor” Inst. Of Image Communicational&Information Processing, Shanghai Jiaotong Univ., Shanghai 200030, China.
[4] Dean P. Kolba, and Thomas W. Parks, “A Prime Factor FFT Algorithm Using High-Speed Convolution,” IEEE Transactions on Acoustics, Speech, and Signal Processing, Vol. ASSP-25, No. 4, August 1977.
[5] S. He and M. Torkelson, “Designing Pipeline FFT Processor for OFDM (de)Modulation,” in Proc. URSI Int. Symp. Signals, Systems, and Electronics, vol.29, Oct.1998,pp.257-262.
[6] Y.-T. Lin, P.-Y. Tsai and T.-D. Chiyeh, “Low-power variable-length fast Fourier transform processor,” IEEE Proc.-Computer. Digit. Tech., Vol. 152, No. 4, pp 499-506, July 2005.
[7] Sang Yoon Park, Nam Ik Cho, Sang Uk Lee, Kichul Kim, Jisung Oh, “Design of 2K/4K/8K-point FFT processor based on CORDIC algorithm in OFDM receiver” in IEEE Communications, Computers and signal Processing, Vol.2, pp. 457-460, Aug. 2001.
[8] Jen-Chih Kuo, Ching-Hua Wen, Chih-Hsiu Lin, An-Yeu(Andy) Wu, “VLSI Design of a Variable-Length FFT/IFFT Processor for OFDM-Based Communication Systems,” in EURASIP Journal on Applied Signal Processing 2003:13, 1306-1316.
[9] Hu, Y.H.: “The Quantization effects of CORDIC algorithm,” IEEE Trans. Signal Process., 1992, Vol.40, No. 4, pp. 834-844.
[10] Stefan Johansson, S. He and Peter Nilsson, “Wordlength optimization of a Pipeline FFT Processor,” In Proc. Symp. Circuits and Systems, Vol.1, pp.501-503, Aug. 1999.
[11] Heiko Schmidt and Karl-Dirk Kammeyer, “Quantization and its effects on OFDM concepts for Wireless Indoor applications,”
[12] Bass, B.M.: “A low-power, high-performance, 1024-point FFT processor,” IEEE J. Solid-State Circuits, 1999, Vol. 34, (3), pp. 380-387
[13] Chung-Ping Hung, Sau-Gee Chen and Kun-Lung Chen, “Design of an efficient
variable-length FFT processor,” IEEE ISCAS, Vol. 2, pp. 833-836, May 2004.
[14] Yu-Wei Lin, Hsung-Yu Liu, and Chen-Yi Lee, “A Dynamic Scaling FFT Processor for DVB-T Applications.” IEEE Journal of solid-state circuits. Vol. 39, No. 11, November 2004.
[15] Wei-Hsin Chang, Truong Nguyen, “An OFDM-specified lossless FFT architecture,” IEEE Transactions on circuits and systems -I: Regular papers, Vol. 53, No. 6, JUNE 2006
[16] Chua-Chin Wang, Jian-Ming Huang, and Hsian-Chang Cheng, “A 2K/8K Mode
Small-Area FFT Processor for OFDM Demodulation of DVB-T Receivers, ”IEEE
Transactions on Consumer Electronics, Vol. 51, No. 1, pp. 28-32, February 2005.
[17] Sang Yoon Park and Nam Ik Cho, “Fixed-point error analysis of CORDIC processor base on the variance propagation formula,” IEEE Trans. on Circuits and System, Vol. 51, No. 3, March 2004.
[18] Robert Michael Owens and Joseph JA’JA’, “A VLSI Chip for the Winograd / Prime Factor Algorithm to Compute the Discrete Fourier Transform,”IEEE Trans. On Acoustics, Speech, and Signal Processing, VOL. ASSP-34, NO. 4, AUGUST 1986.
[19] Harvey F. Silverman, “An Introduction to Programming the Winograd Fourier Transform Algorithm,” IEEE Transactions on Acoustics, Speech, and Signal Processing, Vol. ASSP-25, No. 2, April 1977.
[20] Zhi-Xing Tang, Yu-Peng Hu, Chang-Yong Pan, and Lin Yang, “Design of a 3780-Point IFFT Processor for TDS-OFDM, ” IEEE Transactions on Broadcasting, Vol. 48, No. 1, March 2002.