稀疏碼多工接收使用複數維度碼字傳遞使用者資訊以提升資源使用率。傳統接收機基於系統稀疏特性採取訊息傳遞演算法進行解碼，擁有解碼良好效能。然而由於其複雜度隨碼簿大小呈現指數上升趨勢，以硬體之實時實現仍需極高的硬體資源。源於機器學習領域之期望值傳播演算法因而被應用於稀疏碼多工解碼器，並將複雜度成長曲線由指數轉為線性，使其硬體實現可行性大幅提升。本論文首先提出方法將期望值傳播演算法分解成三面向進行解析，並分別由使用者定義門檻，使系統在達到使用者要求效能下節省非必要之更新運算以降低運算複雜度。其中使用者端終止技術會偵測事後機率收斂程度以停止不必要更新，但其必須加上遞迴次數限制以避免結果誤判。天線端終止技術則透過偵測具備較強通道增益之接收天線並停止該邊緣之更新運算。碼簿縮減方法將自動偵測具備較高可能性之存活碼字並僅將可能解列入事後機率運算。就模擬結果論之，提出方法可在不同門檻設定下達成不同效能及複雜度之平衡。此外，本論文亦實現提出方法之硬體設計，實現之系統架構為：具備4根接收天線、總遞迴次數為4次、保留遞迴次數為2次並且使用16點碼簿之上行系統。利用比較器及閘時鐘電路實現門檻設置，並使用硬體共用技巧取代碼簿縮減方法，使效能達到傳統事後機率運算之同時將RN運算元、天線機率運算元和事後機率運算元之乘法運算分別降低了67%、75%、75%。合成結果顯示可操作最高頻率為156.25MHz並且最高吞吐量可達193.97MBps，邏輯閘數為1377.9K，而透過終止技術的設定，在0.9V的電壓與最高操作時脈下可將功耗從460.6mW降低至254.1mW。

Sparse code multiple access (SCMA) uses multi-dimensional sparse codewords to transmit user data and increases utilization of resources. Conventional decoder adopts massage passing algorithm (MPA) to recover user data based on the sparse property, and achieves good performance. However, the complexity grows exponen-tially as the codebook size increases. Expectation propagation algorithm (EPA), de-rived from machine learning (ML), has been proposed for SCMA decoding and has turned the complexity from exponential growth to linear growth. Thus, it is much suitable for implementation. In this paper, we propose convergence-aware EPA, which incorporates three termination schemes with user defined thresholds respec-tively so that the decoder can stop unnecessary calculations to reduce complexity. The user termination scheme must be combined with the iteration constraint to avoid misjudgement. The antenna termination scheme can stop the computations related with certain antennas having strong channel gains. Only possible codewords are con-sidered in the codebook reduction scheme to eliminate unnecessary calculations for posterior probability. From simulation results, we show that the proposed method can strike a balance between complexity and performance with different threshold set-tings. Furthermore, the hardware of the EPA decoder is implemented supporting 4 receive antennas and, 4 iterations given a 16-point codebook. The gated clock design is applied to realize the early termination. Hardware sharing method helps to reduce the complexity of RN computation units, antenna probability computation units and posterior probability computation units for about 67%, 75%, and 75% with the same performance. The synthesis result shows that maximum operation frequency and throughput of our work are 156.25MHz and 193.97Mbps, respectively. With the ter-mination schemes, the power consumption is reduced from 460.6mW to 254.1mW at 0.9V supply voltage and 156.25MHz operating frequency.

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