在本研究中，我們延續本實驗室在開發一鐵電積體被動元件製程上的努力；我們對具矽基板貫孔之可變鐵電電容的製程進行改善，並且發展了矽化鉻薄膜電阻之製程。
採平行板結構的鐵電可變電容具有高電容密度、高可調度、低操作電壓等優點，然而其品質因子因下電極厚度薄而受限。本實驗室過去於高電阻率矽基板上開發具矽基板貫孔之鐵電可變電容；我們以從背面蝕刻矽基板方式來揭露下電極，續以電鍍金方式來增厚下電極，以期提升其品質因子。然而，量測結果顯示，電容品質因子不高，且製程良率偏低。我們發現，量測品質因子不高原因之一為高電阻率矽基板並未呈現高電阻率之特性，導致包含於量測中的GSG接腳造成較大的微波損耗；而製程良率低的主因則為背面貫孔蝕刻不均勻。
我們參考文獻得知，高電阻率矽基板原生氧化層下會有移動電子層的形成，導致實用上其電阻率不如預期地高；而以氬離子轟擊矽基板表面可使之變為非晶矽，便不會形成移動電子層，即可降低GSG接腳造成之損耗。我們採用此摻雜氬的方法將矽基板之等效電阻率由45 Ω-cm提升至150 Ω-cm。
而在背面貫孔製程良率的改善方面，原先背面貫孔製程只旋塗一層KMPR 1025光阻，然而光阻無法去除乾淨，造成蝕刻後表面平坦度不佳；在本論文中，我們在旋塗KMPR 1025前先旋塗一層LOR 5A，即可將光阻完全去除，提升表面平坦度及貫孔的均勻度。
最後，我們也開發了矽化鉻薄膜電阻製程。矽化鉻薄膜電阻常用於微波電路中的偏壓電阻。矽化鉻薄膜以射頻離子濺鍍機沉積，使用的靶材材料為CrSi2。量測結果顯示，在矽化鉻膜厚為50 nm的情況下，片電阻值約為1–1.5 kΩ/□。而由膜厚為50 nm、100 nm及200 nm的電阻量測結果來推算，我們所製作的矽化鉻薄膜電阻率約為4000–6000 μΩ-cm。
在本論文中，我們成功地藉由摻雜氬來降低了GSG接腳造成之損耗；此外，我們也改善矽基板貫孔的均勻度，並且開發了矽化鉻薄膜電阻。這些製程的進展，使本實驗室所開發的鐵電積體被動元件製程更加完善。

In this work, we continue the efforts of our lab on the development of a ferroelectric-based integrated passive device (IPD) process. We improve the fabrication process for the ferroelectric varactors with through substrate vias (TSVs) on silicon and also develop the fabrication process for chromium silicide thin-film resistors.
The advantages of ferroelectric varactors that adopt parallel-plate structure include high capacitance density, high tunability, and low bias voltage. However, their quality factors are limited by the thin bottom electrodes. We previously developed ferroelectric varactors with TSVs on high-resistivity silicon. The approach is to expose the bottom electrodes of the ferroelectric varactors by etching silicon substrate from backside and then thicken the bottom electrodes by gold electroplating. However, the measured quality factor is not as high as expected and the yield of the process is low. One of the reasons that result in the low quality factor is that the high-resistivity silicon substrate does not exhibit the expected high-resistivity property. Consequently, the microwave loss caused by the GSG (ground-signal-ground) pad becomes unexpectedly high. As for the low yield, the major reason is the poor uniformity of the backside vias.
From previous literatures, it is known that there is a mobile electron layer beneath the native oxide of a high-resistivity silicon substrate, causing that the resistivity is not as high as expected in practice. It is also known that, by bombarding the substrate surface with argon ions, the silicon surface would become amorphous. As a result, the mobile electron layer would not be formed and therefore the microwave loss of the GSG pad is reduced. By adopting the technique of dosing argon, we increase the resistivity of the silicon substrate from 45 Ω-cm to 150 Ω-cm.
As for the improvement of the fabrication process for the backside vias, our original recipe for silicon etching only contains one KMPR 1025 photoresist layer. Unfortunately, it is proven difficult to completely remove the photoresist. Because of the photoresist residue, the surface becomes quite rough. In this work, we spin on a layer of LOR 5A photoresist prior to the KMPR 1025. By doing so, we can completely strip off the photoresists, thereby reducing the surface roughness and improving the uniformity of the backside vias.
Finally, we also develop a fabrication process for chromium silicide thin-film resistors, which are commonly used for bias resistors in microwave circuits. The chromium silicide thin films are deposited using RF sputtering and the target used in the sputter is CrSi2. Measurement results show that the sheet resistance of 50-nm chromium silicide thin film is around 1–1.5 kΩ/□. From the measured data of the resistors with film thickness of 50 nm, 100 nm, and 200 nm, calculated that the resistivity of the chromium silicide thin film we deposit is around 4000–6000 μΩ-cm.
In this thesis, we successfully reduce the microwave loss caused by the GSG pads by dosing Ar in the high-resistivity silicon substrate. We also successfully improve the uniformity of the TSVs on silicon. Finally, we develop the process for fabricating chromium silicide resistors. Through these advances in the fabrication process, we make the ferroelectric IPD process developed by our lab more complete.

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